RC32112A000GN2#KB0 - Renesas Electronics

Description: The RC32112A regenerates and distributes ultra-low jitter clock outputs and features up to 6 independent frequency domains that can be either locked to the external reference clock or locked to a free-run crystal or oscillator. Digital PLLs (DPLLs) support hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for: IEEE 1588 clock synthesis; SyncE clock generation; jitter attenuation and radio clock generation including SYSREF g