Showing 25 of 261 results
Filter by Manufacturer
Image | Part Number | D.S | Description | Package Category | Prices / Stock | Model | Action |
---|
Image | Part Number | D.S | Description | Package Category | Prices / Stock | Model | Action | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
72V291L10TFG8
Renesas Electronics
|
1 | The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co | Quad Flat Packages | 72V291L10TFG8 |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V291L10TFG
Renesas Electronics
|
1 | The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co | Quad Flat Packages | 72V291L10TFG |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V293L7-5BC
Renesas Electronics
|
1 | The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes. | BGA | 72V293L7-5BC |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V293L7-5PFGI
Renesas Electronics
|
1 | The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes. | Quad Flat Packages | 72V293L7-5PFGI |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V295L10PFG8
Renesas Electronics
|
1 | The 72V295 is an 128K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data. | Quad Flat Packages | 72V295L10PFG8 |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V293L6PFG
Renesas Electronics
|
1 | The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes. | Quad Flat Packages | 72V293L6PFG |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V295L10PFG
Renesas Electronics
|
1 | The 72V295 is an 128K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data. | Quad Flat Packages | 72V295L10PFG |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V293L7-5BCI
Renesas Electronics
|
1 | The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes. | BGA | 72V293L7-5BCI |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V293L6BC
Renesas Electronics
|
1 | The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes. | BGA | 72V293L6BC |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V291L15TFI8
Renesas Electronics
|
1 | The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co | Quad Flat Packages | 72V291L15TFI8 |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V291L20TF8
Renesas Electronics
|
1 | The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co | Quad Flat Packages | 72V291L20TF8 |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V291L15TFI
Renesas Electronics
|
1 | The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co | Quad Flat Packages | 72V291L15TFI |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V291L20TF
Renesas Electronics
|
1 | The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co | Quad Flat Packages | 72V291L20TF |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V291L10TF
Renesas Electronics
|
1 | The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co | Quad Flat Packages | 72V291L10TF |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V291L10TF8
Renesas Electronics
|
1 | The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co | Quad Flat Packages | 72V291L10TF8 |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V291L15TF8
Renesas Electronics
|
1 | The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co | Quad Flat Packages | 72V291L15TF8 |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V291L15TF
Renesas Electronics
|
1 | The 72V291 is a 128K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72291 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle co | Quad Flat Packages | 72V291L15TF |
3
|
Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V293L7-5PFG
Integrated Device Technology Inc
|
1 | FIFO, 64KX18, 5ns, Synchronous, CMOS, PQFP80, GREEN, PLASTIC, TQFP-80 | 72V293L7-5PFG |
0
|
Build or Request | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V293L6BCG
Integrated Device Technology Inc
|
1 | FIFO, 64KX18, 4ns, Synchronous, CMOS, PBGA100, 11 X 11 MM, 1 MM PITCH, GREEN, BGA-100 | 72V293L6BCG |
0
|
Build or Request | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V293L7-5BCG8
Integrated Device Technology Inc
|
1 | FIFO, 64KX18, 5ns, Synchronous, CMOS, PBGA100, 11 X 11 MM, 1 MM PITCH, GREEN, BGA-100 | 72V293L7-5BCG8 |
0
|
Build or Request | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V293L7-5BCGI8
Renesas Electronics Corporation
|
1 | FIFO, 64KX18, 5ns, Synchronous, CMOS, PBGA100 | 72V293L7-5BCGI8 |
0
|
Build or Request | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V291L15TFI8
Integrated Device Technology Inc
|
1 | TQFP-64, Reel | 72V291L15TFI8 |
0
|
Build or Request | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V291L15TFI9
Integrated Device Technology Inc
|
1 | FIFO, 128KX9, 10ns, Synchronous, CMOS, PQFP64, STQFP-64 | 72V291L15TFI9 |
0
|
Build or Request | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V293L10PFI
Integrated Device Technology Inc
|
1 | TQFP-80, Tray | 72V293L10PFI |
0
|
Build or Request | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
72V293L6PF8
Integrated Device Technology Inc
|
1 | TQFP-80, Reel | 72V293L6PF8 |
0
|
Build or Request | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||