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74HC273D - Toshiba

Description: Buffers & Line Drivers Pb-F CMOS LOGIC IC SERIES SOIC14 Bus Buffer Gate

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74HC273D - Toshiba PCB footprint - Small Outline Packages - Small Outline Packages - SOIC20
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74HC273D - Toshiba  - 3D model - Small Outline Packages - SOIC20
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74HC273D Details

  • Manufacturer Part Number:

    74HC273D

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Not Recommended

  • Package Description:

    SOIC-20

  • HTS Code:

    8542.39.00.60

  • Factory Lead Time:

    20 Weeks

  • Date Of Intro:

    2016-05-24

  • Manufacturer:

    Toshiba America Electronic Components

  • YTEOL:

    3

  • Family:

    HC/UH

  • JESD-30 Code:

    R-PDSO-G20

  • Length:

    12.8 mm

  • Load Capacitance (CL):

    50 pF

  • Logic IC Type:

    D FLIP-FLOP

  • Max Frequency@Nom-Sup:

    24000000 Hz

  • Max I(ol):

    0.004 A

  • Number of Bits:

    8

  • Number of Functions:

    1

  • Number of Terminals:

    20

  • Operating Temperature-Max:

    125 °C

  • Operating Temperature-Min:

    -40 °C

  • Output Polarity:

    TRUE

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    SOP

  • Package Equivalence Code:

    SOP20,.4

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Peak Reflow Temperature (Cel):

    260

  • Prop. Delay@Nom-Sup:

    225 ns

  • Propagation Delay (tpd):

    225 ns

  • Seated Height-Max:

    2.5 mm

  • Supply Voltage-Max (Vsup):

    6 V

  • Supply Voltage-Min (Vsup):

    2 V

  • Supply Voltage-Nom (Vsup):

    4.5 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    AUTOMOTIVE

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    1.27 mm

  • Terminal Position:

    DUAL

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Trigger Type:

    POSITIVE EDGE

  • Width:

    7.5 mm

  • fmax-Min:

    24 MHz

74HC273D Frequently Asked Questions (FAQs)

  • The maximum clock frequency of the 74HC273D is 35 MHz, but it can vary depending on the operating conditions and the quality of the clock signal.
  • The 74HC273D requires a power supply voltage (VCC) of 2.0 to 6.0 volts, and it's recommended to use a decoupling capacitor of 0.1 μF to 1 μF between VCC and GND to reduce noise and ensure stable operation.
  • The 74HC273D can sink or source a maximum current of 25 mA per output, but it's recommended to limit the current to 10 mA or less to ensure reliable operation.
  • The CLR input should be connected to VCC through a pull-up resistor (e.g., 1 kΩ) to ensure that the flip-flops are properly reset. The CLR input should be driven low to reset the flip-flops, and then released to allow normal operation.
  • The propagation delay of the 74HC273D is typically around 10 ns, but it can vary depending on the operating conditions and the load capacitance.

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