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88SE9235A1-NAA2C000 - Marvell

Description: Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller

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88SE9235A1-NAA2C000 - Marvell PCB footprint - Quad Flat No-Lead - Quad Flat No-Lead - 76-pin QFN 9 mm × 9 mm
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88SE9235A1-NAA2C000 - Marvell  - 3D model - Quad Flat No-Lead - 76-pin QFN 9 mm × 9 mm
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88SE9235A1-NAA2C000 Details

  • Manufacturer Part Number:

    88SE9235A1-NAA2C000

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Package Description:

    QFN-76

  • HTS Code:

    8542.31.00.30

  • Date Of Intro:

    2018-05-19

  • Manufacturer:

    Marvell Technology Group Ltd

  • YTEOL:

    8.25

  • Bus Compatibility:

    ATA; SPI; UART

  • Clock Frequency-Max:

    25 MHz

  • Data Transfer Rate-Max:

    625 MBps

  • JESD-30 Code:

    S-XQCC-N76

  • Length:

    9 mm

  • Number of Terminals:

    76

  • Operating Temperature-Max:

    70 °C

  • Package Body Material:

    UNSPECIFIED

  • Package Code:

    HVQCCN

  • Package Equivalence Code:

    LCC76,.35SQ,16

  • Package Shape:

    SQUARE

  • Package Style:

    CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE

  • Seated Height-Max:

    1 mm

  • Supply Current-Max:

    1500 mA

  • Supply Voltage-Max:

    1.05 V

  • Supply Voltage-Min:

    0.95 V

  • Supply Voltage-Nom:

    1 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    COMMERCIAL

  • Terminal Form:

    NO LEAD

  • Terminal Pitch:

    0.4 mm

  • Terminal Position:

    QUAD

  • Width:

    9 mm

  • uPs/uCs/Peripheral ICs Type:

    BUS CONTROLLER, PCI

88SE9235A1-NAA2C000 Frequently Asked Questions (FAQs)

  • The 88SE9235A1-NAA2C000 has an operating temperature range of 0°C to 85°C (commercial temperature range) and -40°C to 85°C (industrial temperature range).
  • The PCIe interface can be configured through the PCIe configuration space, which is accessed through the PCIe configuration cycles. The configuration space is divided into headers, and each header has a specific function. Refer to the PCIe specification and the 88SE9235A1-NAA2C000 datasheet for more information.
  • The 88SE9235A1-NAA2C000 supports PCIe Gen3, which has a maximum data transfer rate of 985 MB/s per lane. Since this chip has 4 lanes, the maximum data transfer rate is 3.94 GB/s.
  • The 88SE9235A1-NAA2C000 has several power management features, including ASPM (Active State Power Management), L1 sub-states, and power gating. Implementing power management involves configuring the chip's power management registers and using the PCIe power management protocol.
  • The reference clock input requires a 25 MHz clock signal with a tolerance of ±100 ppm. The clock signal should be a stable, low-jitter signal to ensure proper operation of the chip.

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88SE9235A1-NAA2C000 Overview

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