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9112AG-16LF - Renesas Electronics

Description: The IDT9112-16 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to 133 MHz.

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9112AG-16LF - Renesas Electronics PCB footprint - Small Outline Packages - Small Outline Packages - pgg8
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9112AG-16LF Details

  • Manufacturer Part Number:

    9112AG-16LF

  • Brand Name:

    Renesas

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    TSSOP

  • Package Description:

    4.40 MM, 0.65 MM PITCH, GREEN, MO-153, TSSOP-8

  • Pin Count:

    8

  • Manufacturer Package Code:

    PGG8

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Renesas Electronics Corporation

  • YTEOL:

    0

  • Family:

    9112

  • Input Conditioning:

    STANDARD

  • JESD-30 Code:

    R-PDSO-G8

  • JESD-609 Code:

    e3

  • Length:

    4.4 mm

  • Logic IC Type:

    PLL BASED CLOCK DRIVER

  • Max I(ol):

    0.025 A

  • Moisture Sensitivity Level:

    1

  • Number of Functions:

    1

  • Number of Terminals:

    8

  • Number of True Outputs:

    5

  • Operating Temperature-Max:

    70 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    TSSOP

  • Package Equivalence Code:

    TSSOP8,.25

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE, THIN PROFILE, SHRINK PITCH

  • Packing Method:

    TUBE

  • Peak Reflow Temperature (Cel):

    260

  • Qualification Status:

    Not Qualified

  • Same Edge Skew-Max (tskwd):

    0.25 ns

  • Seated Height-Max:

    1.2 mm

  • Supply Voltage-Max (Vsup):

    3.6 V

  • Supply Voltage-Min (Vsup):

    3 V

  • Supply Voltage-Nom (Vsup):

    3.3 V

  • Surface Mount:

    YES

  • Temperature Grade:

    COMMERCIAL

  • Terminal Finish:

    MATTE TIN

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.65 mm

  • Terminal Position:

    DUAL

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    3 mm

  • fmax-Min:

    133 MHz

9112AG-16LF Frequently Asked Questions (FAQs)

  • The recommended operating temperature range for the 9112AG-16LF is -40°C to +85°C.
  • To configure the 9112AG-16LF for low-power mode, set the Power-Down (PD) pin high and the Chip Select (CS) pin low. Additionally, ensure that the clock input is stopped or set to a low frequency.
  • The maximum clock frequency supported by the 9112AG-16LF is 16 MHz.
  • To handle bus contention, use a bus arbiter or a multiplexer to ensure that only one device is active on the bus at a time. Additionally, use a pull-up resistor on the bus lines to prevent bus contention.
  • The maximum data retention period for the 9112AG-16LF is 10 years at a temperature of 25°C.

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9112AG-16LF Overview

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