Description:The 9FGL0641/51 devices are 6-output 3.3V PCIe Gen1–5 clock generators. Each output has a dedicated OE# pin supporting PCIe CLKREQ# functionality. Two different spread spectrum levels, in addition to spread off, are supported. The 9FGL0641/51 supports PCIe Gen1–5 Common Clocked architectures (CC), PCIe Separate Reference no-Spread (SRNS) and Separate Reference Independent Spread (SRIS) clocking architectures. For information regarding evaluation boards and material, please contact your local sales represent
Renesas provides a recommended PCB layout guide in their application notes (e.g., AN9834) and design guides (e.g., DG0094). It's essential to follow these guidelines to ensure optimal performance, minimize noise, and reduce EMI.
The 9FGL0641DKILFT has a built-in POR and BOD circuit. To implement POR, connect the VCC pin to a power supply with a suitable decoupling capacitor. For BOD, connect the BOD pin to a voltage divider network that sets the desired brown-out detection threshold. Refer to the datasheet and application notes for more details.
To minimize clock signal degradation, use a low-impedance path, and terminate the clock signal with a suitable resistor (e.g., 22 ohms) close to the clock source. Avoid routing clock signals near noisy signals or power lines. Refer to the datasheet and application notes for more information.
To ensure reliable SPI communication, use a suitable pull-up resistor (e.g., 1 kohm) on the SCK, MOSI, and SS pins. Also, ensure that the slave device is properly powered and initialized before initiating SPI communication. Refer to the datasheet and application notes for more details.
The 9FGL0641DKILFT has a thermal pad on the bottom of the package. Ensure good thermal contact between the thermal pad and a heat sink or a thermal via on the PCB. Follow the recommended thermal design guidelines in the datasheet and application notes to prevent overheating.
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