ASMT-QWBC-NJK0E footprint, schematic symbol and 3D model by Avago Technologies

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ASMT-QWBC-NJK0E Details

Manufacturer Part Number:
ASMT-QWBC-NJK0E
Pbfree Code:
Yes
Rohs Code:
Yes
Part Life Cycle Code:
Active
Package Description:
3.20 X 2.80 MM, 1.90 MM HEIGHT, ROHS COMPLIANT, SMT, PLASTIC, LCC-4
Reach Compliance Code:
Compliant
HTS Code:
8541.40.20.00
Manufacturer:
Avago Technologies
YTEOL:
7
Additional Feature:
HIGH RELIABILITY
Color:
COOL WHITE
Color@Wavelength:
White
Configuration:
SINGLE
Forward Current-Max:
0.15 A
Forward Voltage-Max:
3.8 V
JESD-609 Code:
e4
Mounting Feature:
SURFACE MOUNT
Number of Functions:
1
Number of Terminals:
4
Operating Temperature-Max:
120 °C
Operating Temperature-Min:
-40 °C
Optoelectronic Device Type:
SINGLE COLOR LED
Overall Height:
1.9 mm
Packing Method:
TR, 7 INCH
Reverse Voltage-Max:
4 V
Shape:
ROUND
Size:
2.4 mm
Surface Mount:
YES
Terminal Finish:
Silver (Ag)
Terminal Pitch:
1.5 mm
Viewing Angle:
120 deg

The recommended clock frequency for the ASMT-QWBC-NJK0E is between 250 MHz to 500 MHz, with an optimal frequency of 400 MHz for best performance.
Use a clock signal with low jitter (<100 ps) and ensure the ADC clock is synchronized with the FPGA/DSP clock using a common clock source or a clock buffer.
The recommended input signal amplitude is 2 Vpp differential, with an input impedance of 100 ohms differential. This ensures optimal SNR and linearity.
The ASMT-QWBC-NJK0E outputs 12-bit data in offset binary format. Ensure your FPGA/DSP is configured to accept 12-bit words and perform any necessary data formatting and processing.
The ASMT-QWBC-NJK0E requires a single 1.8V power supply (AVDD) and a separate 3.3V power supply (DVDD) for the digital interface. Ensure power supply noise is minimized to prevent ADC performance degradation.

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