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AT25DF011-SSHN-T - Renesas Electronics

Description: The AT25DF011 is a member of our System Enhancing class of code and data storage solutions. It is designed for all system memory tasks ranging from boot/code shadowing to data logging and includes the 256-byte page Erase feature that enables efficient, lower energy datalogging.

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AT25DF011-SSHN-T - Renesas Electronics PCB footprint - Small Outline Packages - Small Outline Packages - 8S1 – JEDEC SOIC
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AT25DF011-SSHN-T Details

  • Manufacturer Part Number:

    AT25DF011-SSHN-T

  • Brand Name:

    Renesas

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    SOIC-N

  • Package Description:

    SOIC-8

  • Country Of Origin:

    Philippines

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.32.00.51

  • Factory Lead Time:

    18 Weeks

  • Manufacturer:

    Renesas Electronics Corporation

  • YTEOL:

    5

  • Clock Frequency-Max (fCLK):

    104 MHz

  • Data Retention Time-Min:

    20

  • JESD-30 Code:

    R-PDSO-G8

  • JESD-609 Code:

    e3

  • Length:

    4.925 mm

  • Memory Density:

    1048576 bit

  • Memory IC Type:

    FLASH

  • Memory Width:

    8

  • Moisture Sensitivity Level:

    1

  • Number of Functions:

    1

  • Number of Terminals:

    8

  • Number of Words:

    131072 words

  • Number of Words Code:

    128000

  • Operating Mode:

    SYNCHRONOUS

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    128KX8

  • Output Characteristics:

    3-STATE

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    SOP

  • Package Equivalence Code:

    SOP8,.25

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Parallel/Serial:

    SERIAL

  • Programming Voltage:

    1.8 V

  • Seated Height-Max:

    1.75 mm

  • Supply Voltage-Max (Vsup):

    3.6 V

  • Supply Voltage-Min (Vsup):

    1.7 V

  • Supply Voltage-Nom (Vsup):

    1.8 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Matte Tin (Sn)

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    1.27 mm

  • Terminal Position:

    DUAL

  • Type:

    NOR TYPE

  • Width:

    3.9 mm

AT25DF011-SSHN-T Frequently Asked Questions (FAQs)

  • The AT25DF011-SSHN-T has a maximum of 100,000 erase cycles per sector, and 10,000 erase cycles per device.
  • The AT25DF011-SSHN-T has a 256-byte page write buffer. If the buffer overflows, the device will automatically start a new page write cycle, and the excess data will be written to the next page.
  • The recommended power-up sequence is to apply VCC first, followed by the clock signal (SCK), and then the chip select signal (CS). This ensures proper device initialization and prevents unwanted writes or erases.
  • Yes, the AT25DF011-SSHN-T can be used in a multi-master SPI bus configuration. However, it's essential to ensure that only one master device is active at a time to prevent data corruption or bus conflicts.
  • The AT25DF011-SSHN-T has a software-controlled write protection feature. By setting the write protection bits in the status register, the device can be protected against accidental writes or erases.

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