CS47L90-CWZR footprint, schematic symbol and 3D model by Cirrus Logic

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CS47L90-CWZR Details

The recommended power-up sequence is to apply VDD first, followed by VDDA, and then VDDD. This ensures that the internal voltage regulators are powered up correctly.
To configure the CS47L90 for master clock mode, set the MCLK pin as an output by setting the MCLKOE bit in the Clock Control Register (0x10). Then, set the desired clock frequency using the MCLKDIV registers (0x11-0x12).
The ASP (Audio Serial Port) pin is used for audio data transmission, while the ASPEN (ASP Enable) pin is used to enable or disable the ASP interface. ASPEN should be tied high to enable the ASP interface.
To implement a 24-bit audio interface, set the DBF (Data Bus Format) bits in the Audio Interface Control Register (0x20) to 0b11. This configures the device for 24-bit audio data transmission.
The CS47L90 supports clock frequencies up to 50 MHz.

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