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N24RF04DTPT3G - onsemi

Description: Contactless Transmission of Data; ISO 15693 / ISO 18000−3 Mode1 Compliant; Vicinity Range Communication (up to 150 cm); Air Interface Communication at 13.56 MHz (HF); To tag: ASK Modulation with 1.65 Kbit/s or 26.48 Kbit/s Data Rate; From Tag: Load Modulation Using Manchester Coding with 423 kHz and 484 kHz Subcarriers in Low (6.6 Kbit/s) or high (26 Kbit/s) Data Rate Mode. Supports the 53 Kbit/s Data Rate with Fast Commands; Read & Write 32−bit Block Mode; Anti−collision Support; 64−bit Unique Identifier (

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N24RF04DTPT3G - onsemi - PCB symbol
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N24RF04DTPT3G - onsemi PCB footprint - Small Outline Packages - Small Outline Packages - TSSOP8 4.4x3 CASE 948AL ISSUE O
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N24RF04DTPT3G - onsemi - 3D model - Small Outline Packages - TSSOP8 4.4x3 CASE 948AL ISSUE O
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N24RF04DTPT3G Details

  • Manufacturer Part Number:

    N24RF04DTPT3G

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    TSSOP-8

  • Manufacturer Package Code:

    948AL

  • Country Of Origin:

    Thailand

  • HTS Code:

    8542.31.00.30

  • Factory Lead Time:

    14 Weeks

  • Manufacturer:

    onsemi

  • YTEOL:

    0

  • JESD-609 Code:

    e4

  • Moisture Sensitivity Level:

    1

  • Peak Reflow Temperature (Cel):

    260

  • Terminal Finish:

    Nickel/Palladium/Gold (Ni/Pd/Au)

  • Time@Peak Reflow Temperature-Max (s):

    30

  • uPs/uCs/Peripheral ICs Type:

    NFC CONTROLLER

N24RF04DTPT3G Frequently Asked Questions (FAQs)

  • The recommended operating voltage range for the N24RF04DTPT3G is 2.7V to 3.6V, with a typical voltage of 3.0V.
  • To ensure reliable data retention, it's essential to follow the recommended write endurance cycles (typically 100,000 cycles), avoid excessive voltage fluctuations, and maintain a stable operating temperature within the specified range (-40°C to 85°C).
  • The N24RF04DTPT3G supports a maximum clock frequency of 1 MHz, with a typical frequency of 400 kHz.
  • To handle bus contention and arbitration, implement a suitable arbitration mechanism, such as a token-passing protocol or a master-slave architecture, to ensure that only one master device accesses the bus at a time.
  • The WP pin is used to enable or disable write protection for the entire memory array. When WP is low, the device is in write-protect mode, and any write attempts will be ignored.

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