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NCV5104DR2G - onsemi

Description: High Voltage range: up to 600 V; dV/dt Immunity 50 V/nsec; Gate drive supply range from 10 V to 20 V; High and Low drive outputs; Output source / sink current capability: 250 mA / 500 mA; 3.3 V and 5 V input logic compatible; Up to Vcc swing on input pins; Matched propagation delays between both channels; 1 input with internal fixed dead time (520 ns); Under Vcc LockOut (UVLO) for both channels; Pin to pin compatible with Industry standard

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NCV5104DR2G - onsemi PCB footprint - Small Outline Packages - Small Outline Packages - SOIC-8 NB CAST 751-07 ISSUE AK
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NCV5104DR2G - onsemi  - 3D model - Small Outline Packages - SOIC-8 NB CAST 751-07 ISSUE AK
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NCV5104DR2G Details

  • Manufacturer Part Number:

    NCV5104DR2G

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    SOIC-8

  • Manufacturer Package Code:

    751-07

  • Country Of Origin:

    Philippines

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.60

  • Factory Lead Time:

    19 Weeks

  • Manufacturer:

    onsemi

  • YTEOL:

    7

  • Interface IC Type:

    HALF BRIDGE BASED PERIPHERAL DRIVER

  • JESD-30 Code:

    R-PDSO-G8

  • JESD-609 Code:

    e3

  • Moisture Sensitivity Level:

    1

  • Number of Terminals:

    8

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    SOP

  • Package Equivalence Code:

    SOP8,.25

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Peak Reflow Temperature (Cel):

    260

  • Qualification Status:

    Not Qualified

  • Screening Level:

    AEC-Q100

  • Supply Voltage-Nom:

    15 V

  • Surface Mount:

    YES

  • Terminal Finish:

    Matte Tin (Sn) - annealed

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    1.27 mm

  • Terminal Position:

    DUAL

  • Time@Peak Reflow Temperature-Max (s):

    30

NCV5104DR2G Frequently Asked Questions (FAQs)

  • A good PCB layout for optimal thermal performance involves placing the device near a thermal pad or a heat sink, using a 2-layer or 4-layer board, and minimizing the distance between the device and the thermal pad or heat sink.
  • To ensure reliable operation at high temperatures, ensure that the device is operated within the recommended temperature range, use a heat sink or thermal pad, and follow proper PCB design and layout guidelines.
  • Exceeding the maximum junction temperature can lead to reduced device lifespan, decreased performance, and potentially even device failure.
  • To protect the device from EOS, use a transient voltage suppressor (TVS) or a zener diode to clamp voltage transients, and ensure that the device is operated within the recommended voltage range.
  • The recommended storage condition for the device is in a dry, cool place, away from direct sunlight, and in its original packaging or an anti-static bag.

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NCV5104DR2G Overview

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