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S5920Q - AMCC

Description: PCI Product Serial Interface 160-Pin PQFP

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S5920Q - AMCC  - 3D model
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S5920Q Details

  • Manufacturer Part Number:

    S5920Q

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    QFP

  • Package Description:

    28 X 28 MM, 3.37 MM HEIGHT, PLASTIC, QFP-160

  • Pin Count:

    160

  • ECCN Code:

    3A991.a.2

  • HTS Code:

    8542.31.00.30

  • Manufacturer:

    Applied Micro Circuits Corporation

  • YTEOL:

    0

  • Address Bus Width:

    32

  • Clock Frequency-Max:

    33.33 MHz

  • Data Transfer Rate-Max:

    132 MBps

  • External Data Bus Width:

    32

  • JESD-30 Code:

    S-PQFP-G160

  • Length:

    28 mm

  • Number of Terminals:

    160

  • Operating Temperature-Max:

    70 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    QFP

  • Package Equivalence Code:

    QFP160,1.2SQ

  • Package Shape:

    SQUARE

  • Package Style:

    FLATPACK

  • Peak Reflow Temperature (Cel):

    NOT SPECIFIED

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    4.07 mm

  • Supply Current-Max:

    197 mA

  • Supply Voltage-Max:

    5.25 V

  • Supply Voltage-Min:

    4.75 V

  • Supply Voltage-Nom:

    5 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    COMMERCIAL

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.65 mm

  • Terminal Position:

    QUAD

  • Time@Peak Reflow Temperature-Max (s):

    NOT SPECIFIED

  • Width:

    28 mm

  • uPs/uCs/Peripheral ICs Type:

    BUS CONTROLLER, PCI

S5920Q Frequently Asked Questions (FAQs)

  • A 4-layer PCB with a solid ground plane and thermal vias is recommended for optimal thermal performance. The device should be placed near a thermal pad or heat sink to dissipate heat efficiently.
  • Use controlled impedance traces, add series termination resistors, and ensure that the signal return path is as short as possible. Also, use a common clock and ensure that the clock signal is routed close to the data signals.
  • The recommended power-up sequence is to power up the core voltage (VCC) first, followed by the I/O voltage (VCCIO). Ensure that the power supplies are stable before applying clock and input signals.
  • During power-up, ensure that the JTAG interface is in a high-impedance state until the device is fully powered up. During power-down, ensure that the JTAG interface is in a high-impedance state before powering down the device.
  • The recommended settings for the PLL and clocking circuitry can be found in the device's datasheet and application notes. Ensure that the PLL is properly configured and the clock signals are properly routed and terminated.

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S5920Q Overview

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