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TBD62004APG - Toshiba

Description: Gate Drivers DMOS Transistor Array 7-CH, 50V/0.5A

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PCB Footprints
TBD62004APG - Toshiba PCB footprint - Dual-In-Line Packages - Dual-In-Line Packages - DIP-16-P-300-2.54A_2
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3D Models
TBD62004APG - Toshiba  - 3D model - Dual-In-Line Packages - DIP-16-P-300-2.54A_2
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TBD62004APG Details

  • Manufacturer Part Number:

    TBD62004APG

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Package Description:

    DIP-16

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.60

  • Factory Lead Time:

    20 Weeks

  • Manufacturer:

    Toshiba America Electronic Components

  • YTEOL:

    5.62

  • Built-in Protections:

    TRANSIENT

  • Driver Number of Bits:

    1

  • Interface IC Type:

    BUFFER OR INVERTER BASED PERIPHERAL DRIVER

  • JESD-30 Code:

    R-PDIP-T16

  • Length:

    19.25 mm

  • Number of Functions:

    7

  • Number of Terminals:

    16

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Output Current Flow Direction:

    SINK

  • Output Current-Max:

    0.4 A

  • Output Peak Current Limit-Nom:

    0.4 A

  • Output Polarity:

    INVERTED

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    DIP

  • Package Equivalence Code:

    DIP16,.3

  • Package Shape:

    RECTANGULAR

  • Package Style:

    IN-LINE

  • Peak Reflow Temperature (Cel):

    NOT SPECIFIED

  • Seated Height-Max:

    4.45 mm

  • Supply Current-Max:

    0.1 mA

  • Supply Voltage-Max:

    25 V

  • Supply Voltage-Min:

    7 V

  • Supply Voltage-Nom:

    7 V

  • Surface Mount:

    NO

  • Technology:

    DMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Form:

    THROUGH-HOLE

  • Terminal Pitch:

    2.54 mm

  • Terminal Position:

    DUAL

  • Time@Peak Reflow Temperature-Max (s):

    NOT SPECIFIED

  • Turn-off Time:

    0.8 µs

  • Turn-on Time:

    0.4 µs

  • Width:

    7.62 mm

TBD62004APG Frequently Asked Questions (FAQs)

  • The recommended operating voltage range for TBD62004APG is 1.65V to 3.6V.
  • To ensure proper power-on and power-off, it is recommended to follow a power-up sequence of VCC, then VIO, and a power-down sequence of VIO, then VCC.
  • The TBD62004APG supports a maximum clock frequency of 100 MHz.
  • The TBD62004APG has three power management modes: Active, Idle, and Sleep. The device can be put into these modes by asserting the corresponding control signals (e.g., CE, OE, and RST).
  • The TBD62004APG has a latency of 2 clock cycles and an access time of 10 ns (max) for read operations.

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TBD62004APG Overview

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