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TC74HC7292AP(F) - Toshiba

Description: Toshiba TC74HC7292AP(F), Clock Divider 16-Pin

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TC74HC7292AP(F) - Toshiba PCB footprint - Dual-In-Line Packages - Dual-In-Line Packages - FFPF10F150STU
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TC74HC7292AP(F) - Toshiba  - 3D model - Dual-In-Line Packages - FFPF10F150STU
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TC74HC7292AP(F) Details

  • Manufacturer Part Number:

    TC74HC7292AP(F)

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Package Description:

    DIP-16

  • HTS Code:

    8542.39.00.60

  • Manufacturer:

    Toshiba America Electronic Components

  • YTEOL:

    5.35

  • Family:

    HC/UH

  • JESD-30 Code:

    R-PDIP-T16

  • Length:

    19.25 mm

  • Load Capacitance (CL):

    50 pF

  • Logic IC Type:

    PRESCALER

  • Max Frequency@Nom-Sup:

    26000000 Hz

  • Number of Data/Clock Inputs:

    2

  • Number of Functions:

    1

  • Number of Terminals:

    16

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Output Polarity:

    TRUE

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    DIP

  • Package Equivalence Code:

    DIP16,.3

  • Package Shape:

    RECTANGULAR

  • Package Style:

    IN-LINE

  • Power Supply Current-Max (ICC):

    0.04 mA

  • Propagation Delay (tpd):

    530 ns

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    4.45 mm

  • Supply Voltage-Max (Vsup):

    6 V

  • Supply Voltage-Min (Vsup):

    2 V

  • Supply Voltage-Nom (Vsup):

    5 V

  • Surface Mount:

    NO

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Form:

    THROUGH-HOLE

  • Terminal Pitch:

    2.54 mm

  • Terminal Position:

    DUAL

  • Width:

    7.62 mm

  • fmax-Min:

    26 MHz

TC74HC7292AP(F) Frequently Asked Questions (FAQs)

  • The recommended operating voltage range for the TC74HC7292AP(F) is 2.0 V to 5.5 V.
  • To ensure proper power-on and power-off, it is recommended to follow a slow voltage ramp-up and ramp-down sequence, with a minimum rise and fall time of 1 ms.
  • The maximum clock frequency supported by the TC74HC7292AP(F) is 10 MHz.
  • To enter power-down mode, the CE (Chip Enable) pin should be set to a logic high level. In this mode, the internal clock is stopped, and the power consumption is reduced.
  • The OE pin is used to enable or disable the output drivers. When OE is set to a logic low level, the output drivers are enabled, and when OE is set to a logic high level, the output drivers are disabled.

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TC74HC7292AP(F) Overview

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