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TC74HC74AP(F) - Toshiba

Description: Dual D-Type Flip Flop Preset and Clear

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TC74HC74AP(F) - Toshiba PCB footprint - Dual-In-Line Packages - Dual-In-Line Packages - DIP14-P-300-2.54
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TC74HC74AP(F) - Toshiba  - 3D model - Dual-In-Line Packages - DIP14-P-300-2.54
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TC74HC74AP(F) Details

  • Manufacturer Part Number:

    TC74HC74AP(F)

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    DIP

  • Package Description:

    DIP-14

  • Pin Count:

    14

  • HTS Code:

    8542.39.00.60

  • Manufacturer:

    Toshiba America Electronic Components

  • YTEOL:

    5

  • Family:

    HC/UH

  • JESD-30 Code:

    R-PDIP-T14

  • Length:

    19.25 mm

  • Load Capacitance (CL):

    50 pF

  • Logic IC Type:

    D FLIP-FLOP

  • Max Frequency@Nom-Sup:

    25000000 Hz

  • Max I(ol):

    0.004 A

  • Number of Bits:

    1

  • Number of Functions:

    2

  • Number of Terminals:

    14

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Output Polarity:

    COMPLEMENTARY

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    DIP

  • Package Equivalence Code:

    DIP14,.3

  • Package Shape:

    RECTANGULAR

  • Package Style:

    IN-LINE

  • Peak Reflow Temperature (Cel):

    NOT SPECIFIED

  • Propagation Delay (tpd):

    190 ns

  • Seated Height-Max:

    4.45 mm

  • Supply Voltage-Max (Vsup):

    6 V

  • Supply Voltage-Min (Vsup):

    2 V

  • Supply Voltage-Nom (Vsup):

    5 V

  • Surface Mount:

    NO

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Form:

    THROUGH-HOLE

  • Terminal Pitch:

    2.54 mm

  • Terminal Position:

    DUAL

  • Time@Peak Reflow Temperature-Max (s):

    NOT SPECIFIED

  • Trigger Type:

    POSITIVE EDGE

  • Width:

    7.62 mm

  • fmax-Min:

    29 MHz

TC74HC74AP(F) Frequently Asked Questions (FAQs)

  • The recommended operating voltage range for the TC74HC74AP(F) is 2.0V to 6.0V.
  • To ensure the flip-flop is properly reset during power-up, connect the preset (PRE) and clear (CLR) inputs to VCC through a 1kΩ to 10kΩ resistor, and ground them through a 1nF to 10nF capacitor.
  • The maximum clock frequency for the TC74HC74AP(F) is 25MHz at VCC = 5.0V and 10MHz at VCC = 3.0V.
  • The asynchronous preset (PRE) and clear (CLR) inputs should be driven by a signal that is synchronized with the clock signal to avoid metastability issues.
  • The propagation delay time for the TC74HC74AP(F) is typically 15ns at VCC = 5.0V and 25ns at VCC = 3.0V.

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TC74HC74AP(F) Overview

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