SMALL OUTLINE, HEAT SINK/SLUG, VERY VERY THIN PROFILE
Parallel/Serial:
SERIAL
Programming Voltage:
1.8 V
Seated Height-Max:
0.8 mm
Serial Bus Type:
QSPI
Standby Current-Max:
0.0003 A
Supply Current-Max:
0.035 mA
Supply Voltage-Max (Vsup):
1.95 V
Supply Voltage-Min (Vsup):
1.7 V
Supply Voltage-Nom (Vsup):
1.8 V
Surface Mount:
YES
Technology:
CMOS
Terminal Form:
NO LEAD
Terminal Pitch:
1.27 mm
Terminal Position:
DUAL
Type:
SLC NAND TYPE
Width:
6 mm
Write Protection:
HARDWARE/SOFTWARE
W25N02JWZEIF Frequently Asked Questions (FAQs)
The W25N02JWZEIF supports up to 100,000 erase cycles.
The HOLD# signal should be kept high during a write operation to prevent any interruption. If the HOLD# signal is asserted low during a write operation, the write operation will be paused until the HOLD# signal is de-asserted.
The WP# pin is used to prevent accidental writes to the status register. When the WP# pin is asserted low, the status register is write-protected.
The optimal clock frequency depends on the specific application requirements. The W25N02JWZEIF supports clock frequencies up to 104 MHz. It is recommended to consult the datasheet and application notes for guidance on selecting the optimal clock frequency.
The recommended power-up sequence is to apply VCC first, followed by the clock signal (CLK), and then the chip select signal (CS#).
Trust Checks
This model has been built in collaboration with the manufacturer.
Manufacturer Collaborated
This model has been verified by system checks.
System Verified
This model has been reviewed by community users.
Community Approved
Sponsored
W25N02JWZEIF Overview
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