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859S0412BGILF - Renesas Electronics

Description: The 859S0412I is a 4:2 Differential-to-LVPECL/ LVDS Clock Multiplexer which can operate up to 3GHz. The 859S0412I has 4 selectable differential PCLKx/nPCLKx clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The clock select pins have internal pulldown resistors. The CLK_SEL1 pin is the most significant bit and the binary number applied to the select pins

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PCB Footprints
859S0412BGILF - Renesas Electronics PCB footprint - Small Outline Packages - Small Outline Packages - PGG20
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859S0412BGILF - Renesas Electronics  - 3D model - Small Outline Packages - PGG20
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859S0412BGILF Details

  • Manufacturer Part Number:

    859S0412BGILF

  • Brand Name:

    Renesas

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    TSSOP

  • Package Description:

    TSSOP-20

  • Pin Count:

    20

  • Manufacturer Package Code:

    PGG20

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Renesas Electronics Corporation

  • YTEOL:

    0

  • Additional Feature:

    ALSO OPERATES AT 2.5 V SUPPLY

  • Family:

    859S

  • Input Conditioning:

    DIFFERENTIAL MUX

  • JESD-30 Code:

    R-PDSO-G20

  • JESD-609 Code:

    e3

  • Length:

    6.5 mm

  • Logic IC Type:

    LOW SKEW CLOCK DRIVER

  • Moisture Sensitivity Level:

    1

  • Number of Functions:

    1

  • Number of Terminals:

    20

  • Number of True Outputs:

    2

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    TSSOP

  • Package Equivalence Code:

    TSSOP20,.25

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE, THIN PROFILE, SHRINK PITCH

  • Packing Method:

    TUBE

  • Peak Reflow Temperature (Cel):

    260

  • Power Supply Current-Max (ICC):

    80 mA

  • Prop. Delay@Nom-Sup:

    0.8 ns

  • Propagation Delay (tpd):

    0.8 ns

  • Same Edge Skew-Max (tskwd):

    0.025 ns

  • Seated Height-Max:

    1.2 mm

  • Supply Voltage-Max (Vsup):

    3.465 V

  • Supply Voltage-Min (Vsup):

    3.135 V

  • Supply Voltage-Nom (Vsup):

    3.3 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Terminal Finish:

    Tin (Sn)

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.65 mm

  • Terminal Position:

    DUAL

  • Width:

    4.4 mm

  • fmax-Min:

    3000 MHz

859S0412BGILF Frequently Asked Questions (FAQs)

  • A multi-layer PCB with a solid ground plane and thermal vias is recommended. Ensure a minimum of 1mm clearance around the package for airflow and heat dissipation. A thermal pad on the bottom of the package should be connected to a solid ground plane or a thermal relief pattern.
  • Use a 4-layer PCB with a solid ground plane, and route high-speed signals on the inner layers. Implement a decoupling capacitor network and follow the recommended pinout and signal routing guidelines. Ensure a minimum of 3mm clearance between the package and any nearby metal objects.
  • Power-up sequence: VCC, then VCCIO, then RESET#. Power-down sequence: RESET# low, then VCCIO, then VCC. Ensure a minimum of 10ms delay between power-up and initialization.
  • Handle the device in an ESD-controlled environment. Use anti-static wrist straps, mats, and packaging materials. Store the device in its original packaging or an anti-static bag when not in use.
  • Operate the device within the recommended temperature range (-40°C to 125°C) and voltage range (1.14V to 1.26V). Ensure a stable power supply, and implement thermal monitoring and shutdown mechanisms to prevent overheating.

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859S0412BGILF Overview

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