Description:The 8T73S1802 is a fully integrated clock fanout buffer and frequency divider. The input signal is frequency-divided and then fanned out to one differential LVPECL and one LVCMOS output. Each of the outputs can select its individual divider value from the range of ÷1, ÷2, ÷4 and ÷8. Three control inputs EN, SEL0 and SEL1 (3-level logic) are available to select the frequency dividers and the output enable/disable state. The single-ended LVCMOS output is phase-delayed by 650ps to minimize coupling of LVCMOS s
ALSO OPERATES AT 3.3V SUPPLY, FOR QB O/P FOUT IS 200 MHZ
Family:
8T
Input Conditioning:
DIFFERENTIAL MUX
JESD-30 Code:
S-XQCC-N16
JESD-609 Code:
e3
Length:
3 mm
Logic IC Type:
LOW SKEW CLOCK DRIVER
Moisture Sensitivity Level:
3
Number of Functions:
1
Number of Terminals:
16
Number of True Outputs:
3
Operating Temperature-Max:
85 °C
Operating Temperature-Min:
-40 °C
Output Characteristics:
3-STATE
Package Body Material:
UNSPECIFIED
Package Code:
HVQCCN
Package Shape:
SQUARE
Package Style:
CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Cel):
260
Propagation Delay (tpd):
1.5 ns
Same Edge Skew-Max (tskwd):
1 ns
Seated Height-Max:
1 mm
Supply Voltage-Max (Vsup):
2.625 V
Supply Voltage-Min (Vsup):
2.375 V
Supply Voltage-Nom (Vsup):
2.5 V
Surface Mount:
YES
Temperature Grade:
INDUSTRIAL
Terminal Finish:
Matte Tin (Sn)
Terminal Form:
NO LEAD
Terminal Pitch:
0.5 mm
Terminal Position:
QUAD
Width:
3 mm
fmax-Min:
1000 MHz
8T73S1802NLGI/W Frequently Asked Questions (FAQs)
Renesas provides a recommended PCB layout guide in their application note (APN) documents, which can be found on their website. The guide includes layout considerations for signal integrity, power supply, and thermal management.
To ensure reliable operation, follow the recommended operating conditions and derating guidelines provided in the datasheet. Additionally, consider using thermal management techniques such as heat sinks, thermal interfaces, and airflow management to maintain a stable temperature.
The recommended power-up and power-down sequences can be found in the datasheet or in Renesas' application notes. Generally, it is recommended to power up the device in a specific sequence, such as powering up the core voltage before the I/O voltage, and to power down the device in the reverse sequence.
Renesas provides a troubleshooting guide in their application notes or technical support documents. Common troubleshooting steps include checking the power supply, clock signals, and signal integrity, as well as using debugging tools such as oscilloscopes and logic analyzers.
Yes, Renesas provides guidelines for EMI/EMC design considerations in their application notes. These guidelines include recommendations for PCB layout, component selection, and shielding to minimize electromagnetic interference and ensure compliance with regulatory standards.
Trust Checks
This model has been built in collaboration with the manufacturer.
Manufacturer Collaborated
This model has been verified by system checks.
System Verified
This model has been reviewed by community users.
Community Approved
Sponsored
8T73S1802NLGI/W Overview
Use the download button to access the 8T73S1802NLGI/W schematic symbol, PCB footprint, and 3D model.
To find more CAD model downloads similar to this part, try a partial part number search, like 8T73S,
or try a keyword search, such as Clock Drivers
