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CA91C142D-33CEV - Renesas Electronics

Description: PCI-to-VME Bridge Interface 313-PBGA (35x35)

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CA91C142D-33CEV Details

  • Manufacturer Part Number:

    CA91C142D-33CEV

  • Brand Name:

    Renesas

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    PBGA

  • Pin Count:

    313

  • Manufacturer Package Code:

    BGG313

  • ECCN Code:

    3A991.a.2

  • HTS Code:

    8542.39.00.01

  • Factory Lead Time:

    18 Weeks

  • Manufacturer:

    Renesas Electronics Corporation

  • YTEOL:

    5

  • Address Bus Width:

    64

  • Bus Compatibility:

    PCI

  • Clock Frequency-Max:

    33 MHz

  • Data Transfer Rate-Max:

    70 MBps

  • External Data Bus Width:

    64

  • JESD-30 Code:

    S-PBGA-B313

  • JESD-609 Code:

    e1

  • Length:

    35 mm

  • Moisture Sensitivity Level:

    3

  • Number of Terminals:

    313

  • Operating Temperature-Max:

    70 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA313,25X25,50

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Peak Reflow Temperature (Cel):

    260

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    3.5 mm

  • Supply Voltage-Max:

    5.5 V

  • Supply Voltage-Min:

    4.5 V

  • Supply Voltage-Nom:

    5 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    COMMERCIAL

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    2.54 mm

  • Terminal Position:

    BOTTOM

  • Width:

    35 mm

  • uPs/uCs/Peripheral ICs Type:

    VME BUS CONTROLLER

CA91C142D-33CEV Frequently Asked Questions (FAQs)

  • The recommended operating voltage range for the CA91C142D-33CEV is 2.7V to 3.6V.
  • The CA91C142D-33CEV can be configured to use an external clock source or an internal clock source. To use an external clock source, connect the clock signal to the XIN pin and set the CKS bit in the SYSCR register to 0. To use an internal clock source, set the CKS bit to 1 and configure the internal clock frequency using the FREQ bits in the SYSCR register.
  • The maximum frequency of the CA91C142D-33CEV is 33.33 MHz.
  • The CA91C142D-33CEV can be reset by asserting the RESET pin low for at least 2 clock cycles. The device will also reset automatically when the power supply voltage falls below the minimum operating voltage.
  • The WDT is a timer that resets the device if it does not receive a reset signal within a certain time period. This is used to prevent the device from getting stuck in an infinite loop or other abnormal operation.

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CA91C142D-33CEV Overview

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