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CGHV27030S - Wolfspeed

Description: RF JFET Transistors GaN HEMT DC-6.0GHz, 30 Watt

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PCB Footprints
CGHV27030S - Wolfspeed PCB footprint - Small Outline No-lead - Small Outline No-lead - CGHV27030S
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3D Models
CGHV27030S - Wolfspeed  - 3D model - Small Outline No-lead - CGHV27030S
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CGHV27030S Details

  • Manufacturer Part Number:

    CGHV27030S

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Transferred

  • ECCN Code:

    EAR99

  • Manufacturer:

    Wolfspeed

  • Moisture Sensitivity Level:

    3

  • Peak Reflow Temperature (Cel):

    NOT SPECIFIED

  • Time@Peak Reflow Temperature-Max (s):

    NOT SPECIFIED

CGHV27030S Frequently Asked Questions (FAQs)

  • A good PCB layout should ensure minimal thermal resistance, use a thermal via array, and have a solid copper fill on the backside of the board. A heat sink or thermal interface material can be used to improve heat dissipation. Refer to Wolfspeed's application notes for more details.
  • Use proper ESD handling and storage procedures, such as using an ESD wrist strap, mat, or storage bags. Ensure that the device is handled in a static-safe environment, and avoid touching the device pins or die.
  • A gate drive voltage of +2V to +5V is recommended, with a current limit of 10mA to 20mA. A resistive divider or a dedicated gate driver IC can be used to set the gate voltage. Refer to Wolfspeed's application notes for specific biasing configurations.
  • Monitor the device's voltage, current, and temperature to ensure they are within the specified limits. Use a thermal management strategy to keep the junction temperature below 150°C. Refer to the datasheet for the SOA graph and thermal derating curves.
  • Use a gold wire bond with a diameter of 0.7mil to 1.0mil, and a bond force of 10gf to 20gf. Ensure the die attach material is suitable for high-power applications, and follow Wolfspeed's recommended die attach procedures.

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