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EP2S60F1020C4N - Intel

Description: FPGA - Field Programmable Gate Array FPGA - Stratix II 30 22 LABs 718 IOs

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PCB Footprints
EP2S60F1020C4N - Intel PCB footprint - BGA - BGA - 1020-FBGA (33x33)
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3D Models
EP2S60F1020C4N - Intel  - 3D model - BGA - 1020-FBGA (33x33)
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EP2S60F1020C4N Details

  • Manufacturer Part Number:

    EP2S60F1020C4N

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    33 X 33 MM, 1 MM PITCH, FBGA-1020

  • HTS Code:

    8542.31.00.60

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    0

  • Clock Frequency-Max:

    717 MHz

  • Combinatorial Delay of a CLB-Max:

    5.117 ns

  • JESD-30 Code:

    S-PBGA-B1020

  • JESD-609 Code:

    e1

  • Length:

    33 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    24176

  • Number of Inputs:

    718

  • Number of Logic Cells:

    60440

  • Number of Outputs:

    710

  • Number of Terminals:

    1020

  • Operating Temperature-Max:

    85 °C

  • Organization:

    24176 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA672,26X26,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    3.5 mm

  • Supply Voltage-Max:

    1.25 V

  • Supply Voltage-Min:

    1.15 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS, 90 nm

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Width:

    33 mm

EP2S60F1020C4N Frequently Asked Questions (FAQs)

  • The maximum operating temperature range for EP2S60F1020C4N is -40°C to 100°C.
  • A reliable POR circuit can be implemented using a voltage supervisor IC, such as the MAX809, which can detect power-on and power-down sequences and generate a reset signal to the FPGA.
  • The recommended clocking scheme for EP2S60F1020C4N is to use a single clock source, such as a crystal oscillator, and distribute it to the FPGA using a clock distribution network.
  • Optimize the pin-out and floorplanning by grouping related signals together, minimizing signal routing, and using the FPGA's built-in features, such as the I/O banks and clock regions.
  • Follow guidelines for high-speed PCB design, such as using controlled impedance traces, minimizing signal reflections, and using shielding and grounding techniques to reduce EMI.

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EP2S60F1020C4N Overview

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Image Part Number Model
Part Image EP2S60F1020C4N Altera Corporation

Field Programmable Gate Array, 24176 CLBs, 717MHz, 60440-Cell, CMOS, PBGA1020

Part Image EP2S60F1020I4 Altera Corporation

Field Programmable Gate Array, 24176 CLBs, 717MHz, 60440-Cell, CMOS, PBGA1020

Part Image EP2S60F1020C4 Intel Corporation

Field Programmable Gate Array, 24176 CLBs, 717MHz, 60440-Cell, CMOS, PBGA1020

Part Image EP2S60F1020I4N Intel Corporation

Field Programmable Gate Array, 3022 CLBs, 717MHz, 60440-Cell, CMOS, PBGA1020

Part Image EP2S60F1020I4 Intel Corporation

Field Programmable Gate Array, 24176 CLBs, 717MHz, 60440-Cell, CMOS, PBGA1020

For a full list of alternate parts for EP2S60F1020C4N, check out Findchips.com