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IRL40B212 - Infineon

Description: MOSFET 40V, 195A, 1.9 mOhm 91 nC Qg, Logic Lvl

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PCB Footprints
IRL40B212 - Infineon PCB footprint - Transistor Outline, Vertical - Transistor Outline, Vertical - TO-220AB
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3D Models
IRL40B212 - Infineon  - 3D model - Transistor Outline, Vertical - TO-220AB
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IRL40B212 Details

  • Manufacturer Part Number:

    IRL40B212

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • ECCN Code:

    EAR99

  • HTS Code:

    8541.29.00.95

  • Factory Lead Time:

    52 Weeks

  • Manufacturer:

    Infineon Technologies AG

  • YTEOL:

    0

  • Avalanche Energy Rating (Eas):

    790 mJ

  • Configuration:

    SINGLE WITH BUILT-IN DIODE

  • DS Breakdown Voltage-Min:

    40 V

  • Drain Current-Max (ID):

    254 A

  • Drain-source On Resistance-Max:

    0.0019 Ω

  • FET Technology:

    METAL-OXIDE SEMICONDUCTOR

  • Feedback Cap-Max (Crss):

    790 pF

  • JEDEC-95 Code:

    TO-220AB

  • JESD-30 Code:

    R-PSFM-T3

  • Number of Elements:

    1

  • Number of Terminals:

    3

  • Operating Mode:

    ENHANCEMENT MODE

  • Operating Temperature-Max:

    175 °C

  • Operating Temperature-Min:

    -55 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    FLANGE MOUNT

  • Peak Reflow Temperature (Cel):

    NOT SPECIFIED

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    231 W

  • Pulsed Drain Current-Max (IDM):

    990 A

  • Surface Mount:

    NO

  • Terminal Form:

    THROUGH-HOLE

  • Terminal Position:

    SINGLE

  • Time@Peak Reflow Temperature-Max (s):

    NOT SPECIFIED

  • Transistor Application:

    SWITCHING

  • Transistor Element Material:

    SILICON

IRL40B212 Frequently Asked Questions (FAQs)

  • The maximum operating temperature range for the IRL40B212 is -55°C to 175°C.
  • To ensure proper biasing, the gate-source voltage (Vgs) should be between 2V and 10V, and the drain-source voltage (Vds) should be between 1V and 40V.
  • To minimize parasitic inductance, it is recommended to use a compact PCB layout with short, wide traces, and to place the device close to the power source. Additionally, using a ground plane and decoupling capacitors can help reduce parasitic inductance.
  • To protect the IRL40B212 from ESD, it is recommended to handle the device in an ESD-controlled environment, use ESD-protective packaging, and follow proper handling and storage procedures.
  • The maximum current rating for the IRL40B212 is 40A.

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IRL40B212 Overview

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