NB3N1900KMNTWG - onsemi
Description: Fixed Feedback Path for Lowest Input−to−Output Delay; Eight Dedicated OE# Pins for Hardware Control of Outputs; PLL Bypass Configurable for PLL or Fanout Operation; Selectable PLL Bandwidth; Spread Spectrum Compatible: Tracks Input Clock Spreading for Low EMI; SMBus Programmable Configurations; 100 MHz and 133 MHz PLL Mode to Meet the Next Generation PCIe Gen2 / Gen 3 /Gen 4 and Intel QPI & UPI Phase Jitter; 2 Tri−Level Addresses Selection (Nine SMBUS Addresses); Cycle−to−Cycle Jitter: < 50 ps; Output−to−Ou
ECAD model is currently unavailable for this part
