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PSMN4R0-25YLC,115 - Nexperia

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PSMN4R0-25YLC,115 Details

  • Manufacturer Part Number:

    PSMN4R0-25YLC,115

  • Brand Name:

    Nexperia

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    SOIC

  • Package Description:

    LFPAK-4

  • Pin Count:

    4

  • Manufacturer Package Code:

    SOT669

  • Country Of Origin:

    Philippines

  • ECCN Code:

    EAR99

  • Factory Lead Time:

    16 Weeks

  • Manufacturer:

    Nexperia

  • YTEOL:

    5.3

  • Additional Feature:

    HIGH RELIABILITY

  • Avalanche Energy Rating (Eas):

    17.4 mJ

  • Case Connection:

    DRAIN

  • Configuration:

    SINGLE WITH BUILT-IN DIODE

  • DS Breakdown Voltage-Min:

    25 V

  • Drain Current-Max (ID):

    84 A

  • Drain-source On Resistance-Max:

    0.0058 Ω

  • FET Technology:

    METAL-OXIDE SEMICONDUCTOR

  • Feedback Cap-Max (Crss):

    119 pF

  • JEDEC-95 Code:

    MO-235

  • JESD-30 Code:

    R-PSSO-G4

  • JESD-609 Code:

    e3

  • Moisture Sensitivity Level:

    1

  • Number of Elements:

    1

  • Number of Terminals:

    4

  • Operating Mode:

    ENHANCEMENT MODE

  • Operating Temperature-Max:

    175 °C

  • Operating Temperature-Min:

    -55 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Peak Reflow Temperature (Cel):

    260

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    61 W

  • Pulsed Drain Current-Max (IDM):

    336 A

  • Reference Standard:

    IEC-60134

  • Surface Mount:

    YES

  • Terminal Finish:

    Tin (Sn)

  • Terminal Form:

    GULL WING

  • Terminal Position:

    SINGLE

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Transistor Application:

    SWITCHING

  • Transistor Element Material:

    SILICON

PSMN4R0-25YLC,115 Frequently Asked Questions (FAQs)

  • The recommended PCB footprint for PSMN4R0-25YLC,115 is a D2PAK (TO-263) package with a minimum pad size of 4.5mm x 3.5mm and a thermal pad size of 2.5mm x 2.5mm.
  • To ensure reliable operation in high-temperature environments, it's essential to follow proper thermal design and layout guidelines, including providing adequate heat sinking, using thermal interface materials, and minimizing thermal resistance.
  • The maximum allowed voltage on the gate of PSMN4R0-25YLC,115 is ±20V, with a recommended maximum voltage of 15V to ensure reliable operation and prevent damage.
  • Yes, PSMN4R0-25YLC,115 is suitable for high-frequency switching applications up to 100 kHz, but it's essential to consider the device's switching characteristics, such as rise and fall times, and ensure proper layout and decoupling to minimize ringing and EMI.
  • To protect PSMN4R0-25YLC,115 from ESD, follow proper handling and storage procedures, use ESD-safe materials and equipment, and consider adding ESD protection devices, such as TVS diodes or ESD arrays, in the circuit design.

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PSMN4R0-25YLC,115 Overview

Use the download button to access the PSMN4R0-25YLC,115 3D model. You can still request or build the schematic symbol and PCB footprint by using the respective build or request forms on this page.
To find more CAD model downloads similar to this part, try a partial part number search, like PSMN4, or try a keyword search, such as Power Field-Effect Transistors

About Nexperia

Nexperia is a leading global player in the semiconductor industry. Specializing in essential electronic components, Nexperia offers a diverse range of products including discrete components, MOSFETs, logic ICs, and analog ICs. These components are integral to a multitude of applications across automotive, industrial, consumer electronics, and computing sectors, where reliability, performance, and efficiency are paramount.

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