QED123 footprint, schematic symbol and 3D model by onsemi

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QED123 Details

A 4-layer PCB with a solid ground plane and a separate power plane is recommended. Keep the input and output traces short and away from each other to minimize noise coupling.
The QED123 requires a bias voltage of 5V ± 10% on the VCC pin. Ensure the bias voltage is stable and noise-free, and decouple the VCC pin with a 10uF capacitor to ground.
The maximum allowable power dissipation for the QED123 is 1.5W. Ensure proper heat sinking and thermal management to prevent overheating.
The QED123 is rated for operation up to 125°C. However, the device's performance and reliability may degrade at high temperatures. Ensure proper thermal management and consider derating the device for high-temperature applications.
Use an oscilloscope to monitor the input and output signals. Check for proper biasing, decoupling, and PCB layout. Verify the input signal meets the recommended amplitude and frequency specifications.

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