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XC7VX690T-2FFG1761I - AMD

Description: FPGA, VIRTEX-7, 850 I/O, FCBGA-1761; No. of Logic Blocks:108300; No. of Macrocells:693120; FPGA Family:Virtex-7; Logic Case Style:FCBGA; No. of Pins:1761Pins; No. of Speed Grades:2; Total RAM Bits:52920Kbit; No. of I/O s:850I/O s; RoHS Compliant: Yes

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XC7VX690T-2FFG1761I Details

  • Manufacturer Part Number:

    XC7VX690T-2FFG1761I

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Package Description:

    BGA-1761

  • HTS Code:

    8542.31.00.60

  • Factory Lead Time:

    16 Weeks

  • Manufacturer:

    AMD

  • YTEOL:

    14

  • Clock Frequency-Max:

    1818 MHz

  • Combinatorial Delay of a CLB-Max:

    0.61 ns

  • JESD-30 Code:

    S-PBGA-B1761

  • JESD-609 Code:

    e1

  • Length:

    42.5 mm

  • Moisture Sensitivity Level:

    4

  • Number of CLBs:

    54150

  • Number of Inputs:

    850

  • Number of Logic Cells:

    693120

  • Number of Outputs:

    850

  • Number of Terminals:

    1761

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    54150 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA1760,42X42,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Peak Reflow Temperature (Cel):

    245

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    3.5 mm

  • Supply Voltage-Max:

    1.03 V

  • Supply Voltage-Min:

    0.97 V

  • Supply Voltage-Nom:

    1 V

  • Surface Mount:

    YES

  • Technology:

    CMOS, 28 nm

  • Terminal Finish:

    Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    42.5 mm

XC7VX690T-2FFG1761I Frequently Asked Questions (FAQs)

  • The maximum power consumption is approximately 12W, but it depends on the specific design and usage.
  • Use the Xilinx Power Estimator (XPE) tool to estimate power consumption, and optimize your design by reducing clock frequencies, using low-power modes, and minimizing switching activity.
  • The maximum clock frequency is 500 MHz, but it depends on the specific design and the speed grade of the device.
  • Use the Xilinx IBIS-AMI models and the Signal Integrity Wizard in Vivado to analyze and optimize signal integrity on high-speed interfaces like PCIe and Ethernet.
  • Use the Xilinx MIG (Memory Interface Generator) tool to generate a DDR3 memory interface, and follow the Xilinx guidelines for DDR3 implementation.

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XC7VX690T-2FFG1761I Overview

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