DSP56F807PY80E - NXP

Description: Processing Core • Efficient 16-bit 56800 family controller engine with dual Harvard architecture • As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency • Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • Two 36-bit accumulators including extension bits • 16-bit bidirectional barrel shifter • Parallel instruction set with unique processor addressing modes • Hardware DO and REP loops • Three internal address buses and one external address bus • Four internal dat