MC74HC4538ADG - onsemi

Description: Outputs Directly Interface to CMOS, NMOS and TTL; +/- 10% Guaranteed Pulse Width Variation from Part to Part (Using the Same Test Jig); Output Pulse is Independent of the Trigger Pulse Width; In Compliance with the Requirements Defined by JEDEC Standard No. 7A; Chip Complexity: 145 FETs or 36 Equivalent Gates; Output Drive Capability: 10 LSTTL Loads; Operating Voltage Range: 3.0 to 6.0 V; High Noise Immunity Characteristic of CMOS Devices; Low Input Current: 1.0 mA; Unlimited Rise and Fall Times Allowed on