MIMXRT1186CVJ8C - NXP

Description: The Arm Cortex-M7 Core Platform: — 32 KB L1 Instruction Cache and 32 KB L1 Data Cache — Floating Point Unit (FPU) with single-precision and double-precision supports of the Armv7-M architecture FPv5 — Support the Armv7-M Thumb instruction set, defined in the Armv7-M architecture — Integrated Memory Protection Unit (MPU), up to 16 individual protection regions — Up to 512 KB I-TCM and D-TCM in total — Frequency of 800 MHz at 1.1 V (over drive) with Forward Body Biasing (FBB) — ECC support for both Cac