PIC18F26K42T-I/SS - Microchip

Description: C Compiler Optimized RISC Architecture Operating Speed: Up to 64 MHz clock input 62.5 ns minimum instruction cycle Two Direct Memory Access (DMA) Controllers Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR spaces User-programmable source and destination sizes Hardware and software-triggered data transfers System Bus Arbiter with User-Configurable Priorities for Scanner and DMA1/DMA2 with respect to the main line and interrupt execution