PIC18F46Q71-E/MP - Microchip

Description: • C Compiler Optimized RISC Architecture • Operating Speed: – DC – 64 MHz clock input – 62.5 ns minimum instruction cycle • Four Direct Memory Access (DMA) Controllers: – Data transfers to SFR/GPR spaces from either the Program Flash Memory, Data EEPROM or SFR/GPR spaces – User-programmable source and destination sizes – Hardware and software-triggered data transfers • Vectored Interrupt Capability: – Selectable high/low priority – Fixed interrupt latency of three instruction cycles – Programmab