SPC560P50L3BEABR - STMicroelectronics
Description: 64 MHz, single issue, 32-bit CPU core complex (e200z0h) – Compliant with Power Architecture® embedded category – Variable Length Encoding (VLE) ■ Memory organization – Up to 512 KB on-chip code flash memory with ECC and erase/program controller – Additional 64 (4 × 16) KB on-chip data flash memory with ECC for EEPROM emulation – Up to 40 KB on-chip SRAM with ECC ■ Fail safe protection – Programmable watchdog timer – Non-maskable interrupt – Fault collection unit ■ Nexus L2+ interface ■ Inter
