SPC564L54L3CCFQY - STMicroelectronics

Description:  High-performance e200z4d dual core  32-bit Power Architecture® technology CPU  Core frequency as high as 120 MHz  Dual issue five-stage pipeline core  Variable Length Encoding (VLE)  Memory Management Unit (MMU)  4 KB instruction cache with error detection code  Signal processing engine (SPE)  Memory available – 1 MB flash memory with ECC – 128 KB on-chip SRAM with ECC – Built-in RWW capabilities for EEPROM emulation  SIL3/ASILD innovative safety concept: LockStep mode and Fail-saf