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TMPM461F10FG - Toshiba

Description: 1. Arm Cortex-M4 processor with FPU core a. Improved code efficiency has been realized through the use of Thumb®-2 instruction. New 16-bit Thumb instructions for improved program flow New 32-bit Thumb instructions for improved performance New Thumb mixed 16-/32-bit instruction set can produce faster, more efficient code. b. Both high performance and low power consumption have been achieved. [High performance] A 32-bit multiplication (32 × 32 = 32 bits) and multiply-accumulate operation (32 + 32 × 32

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