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10CX105YU484I5G - Intel

Description: FPGA Cyclone® 10 GX Family 104000 Cells 20nm Technology 484-Pin UBGA

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PCB Footprints
10CX105YU484I5G - Intel PCB footprint - BGA - BGA - 484-Pin Ultra FineLine Ball-Grid Array (UBGA) - Flip Chip – Channel Lid - A: 3.25
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3D Models
10CX105YU484I5G - Intel  - 3D model - BGA - 484-Pin Ultra FineLine Ball-Grid Array (UBGA) - Flip Chip – Channel Lid - A: 3.25
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10CX105YU484I5G Details

  • Manufacturer Part Number:

    10CX105YU484I5G

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Transferred

  • Package Description:

    UBGA-484

  • Country Of Origin:

    Mainland China, Malaysia, Taiwan, USA, Vietnam

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    10

  • JESD-30 Code:

    S-PBGA-B484

  • Length:

    19 mm

  • Number of CLBs:

    38000

  • Number of Inputs:

    188

  • Number of Logic Cells:

    104000

  • Number of Outputs:

    188

  • Number of Terminals:

    484

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    38000 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Seated Height-Max:

    2.05 mm

  • Supply Voltage-Max:

    0.93 V

  • Supply Voltage-Min:

    0.87 V

  • Supply Voltage-Nom:

    0.9 V

  • Surface Mount:

    YES

  • Technology:

    20 nm

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.8 mm

  • Terminal Position:

    BOTTOM

  • Width:

    19 mm

10CX105YU484I5G Frequently Asked Questions (FAQs)

  • The 10CX105YU484I5G FPGA has an operating temperature range of 0°C to 100°C (commercial temperature range) and -40°C to 100°C (industrial temperature range).
  • Intel recommends using an external POR circuit with a voltage supervisor IC, such as the MAX809, to ensure a reliable power-on reset. The FPGA's internal POR circuit can also be used, but it may not be as reliable.
  • Intel provides a PCB layout and routing guide for the 10CX105YU484I5G FPGA, which recommends using a 4-layer PCB with a dedicated power plane, and following specific routing guidelines for high-speed signals.
  • To optimize power consumption, use the Intel Quartus Prime software to optimize the design for power, reduce clock frequencies, and use the FPGA's built-in power management features, such as the Power Manager IP core.
  • Intel recommends using 0.1 μF and 10 μF decoupling capacitors, placed as close as possible to the FPGA's power pins, with a maximum distance of 1 inch (2.54 cm) from the FPGA.

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10CX105YU484I5G Overview

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