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859S0212BGILF - Renesas Electronics

Description: The 859S0212I is a 2:2 Differential-to-LVPECL/ LVDS Clock Multiplexer which can operate up to 3GHz. The 859S0212I has 2 selectable differential PCLKx, nPCLKx clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The clock select pin has an internal pulldown resistor.

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859S0212BGILF - Renesas Electronics PCB footprint - Small Outline Packages - Small Outline Packages - PGG16-
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859S0212BGILF - Renesas Electronics  - 3D model - Small Outline Packages - PGG16-
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859S0212BGILF Details

  • Manufacturer Part Number:

    859S0212BGILF

  • Brand Name:

    Renesas

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    TSSOP

  • Package Description:

    TSSOP-16

  • Pin Count:

    16

  • Manufacturer Package Code:

    PGG16

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Renesas Electronics Corporation

  • YTEOL:

    0

  • Additional Feature:

    ALSO OPERATES AT 3.3 V SUPPLY

  • Family:

    859S

  • Input Conditioning:

    DIFFERENTIAL MUX

  • JESD-30 Code:

    R-PDSO-G16

  • JESD-609 Code:

    e3

  • Length:

    5 mm

  • Logic IC Type:

    LOW SKEW CLOCK DRIVER

  • Moisture Sensitivity Level:

    1

  • Number of Functions:

    1

  • Number of Terminals:

    16

  • Number of True Outputs:

    4

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Output Characteristics:

    3-STATE

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    TSSOP

  • Package Equivalence Code:

    TSSOP16,.25

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE, THIN PROFILE, SHRINK PITCH

  • Packing Method:

    TUBE

  • Peak Reflow Temperature (Cel):

    260

  • Power Supply Current-Max (ICC):

    50 mA

  • Prop. Delay@Nom-Sup:

    0.8 ns

  • Propagation Delay (tpd):

    0.8 ns

  • Qualification Status:

    Not Qualified

  • Same Edge Skew-Max (tskwd):

    0.025 ns

  • Seated Height-Max:

    1.2 mm

  • Supply Voltage-Max (Vsup):

    2.625 V

  • Supply Voltage-Min (Vsup):

    2.375 V

  • Supply Voltage-Nom (Vsup):

    2.5 V

  • Surface Mount:

    YES

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    MATTE TIN

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.65 mm

  • Terminal Position:

    DUAL

  • Width:

    4.4 mm

  • fmax-Min:

    3000 MHz

859S0212BGILF Frequently Asked Questions (FAQs)

  • A multi-layer PCB with a solid ground plane and thermal vias is recommended. Ensure a minimum of 1mm clearance around the package for airflow and heat dissipation. Use thermal interface material (TIM) and a heat sink if possible.
  • Use a 4-layer PCB with a solid ground plane, and route critical signals on the inner layers. Implement proper termination, decoupling, and shielding. Follow the datasheet's recommended layout and routing guidelines.
  • The device requires a power-on reset (POR) circuit to ensure proper startup. The recommended power-up sequence is VCC, then VDD, with a ramp-up time of 1ms to 10ms. Consult the datasheet for specific guidelines.
  • Handle the device in an ESD-controlled environment, using wrist straps, mats, and packaging that meet the ESD Association's standards. Store the device in its original packaging or an anti-static bag.
  • The device is rated for a minimum of 10 years of operation at 25°C, with a failure rate of <1 FIT (failure in time). Operating conditions, such as temperature, humidity, and power cycling, can affect lifespan. Consult the datasheet and reliability reports for more information.

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859S0212BGILF Overview

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Part Image 859S0212BGILFT Integrated Device Technology Inc

Low Skew Clock Driver, 859S Series, 4 True Output(s), 0 Inverted Output(s), PDSO16