Description:The 9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when using a low frequency input clock to generate a high frequency output clock. The 9173B contains a phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). The 674-01 can be used as the external feedback divid
Renesas provides a recommended PCB layout guide in their application note (R01AN3804EU0100) which includes thermal design considerations, such as thermal vias, copper pours, and component placement.
Renesas recommends following their thermal design guidelines, using a heat sink if necessary, and ensuring proper airflow around the device. Additionally, consider using a thermistor or thermal sensor to monitor the device temperature.
Renesas recommends using a low-ESR ceramic capacitor (e.g., X5R or X7R) for CIN, with a value between 4.7uF to 10uF. For COUT, use a low-ESR ceramic or electrolytic capacitor with a value between 10uF to 22uF. Ensure the capacitors meet the specified voltage and ripple current ratings.
Renesas provides a feedback network design guide in their application note (R01AN3804EU0100). The guide includes recommendations for resistor and capacitor values, as well as layout considerations to ensure stability and optimal performance.
Renesas recommends following their current rating guidelines and ensuring the device is properly heat-sinked. Additionally, consider using a current sense resistor and monitoring the device temperature to prevent overheating. Be aware of the device's current limit and power dissipation capabilities.
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9173B-15CS08LF Overview
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