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9DB633AGILFT - Renesas Electronics

Description: The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9D

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9DB633AGILFT - Renesas Electronics PCB footprint - Small Outline Packages - Small Outline Packages - TSSOP_28
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9DB633AGILFT Details

  • Manufacturer Part Number:

    9DB633AGILFT

  • Brand Name:

    Renesas

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    TSSOP

  • Pin Count:

    28

  • Manufacturer Package Code:

    PGG28

  • Country Of Origin:

    Taiwan

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Factory Lead Time:

    12 Weeks

  • Manufacturer:

    Renesas Electronics Corporation

  • YTEOL:

    7

  • Family:

    9DB

  • Input Conditioning:

    DIFFERENTIAL

  • JESD-30 Code:

    R-PDSO-G28

  • JESD-609 Code:

    e3

  • Length:

    9.7 mm

  • Logic IC Type:

    PLL BASED CLOCK DRIVER

  • Moisture Sensitivity Level:

    1

  • Number of Functions:

    1

  • Number of Terminals:

    28

  • Number of True Outputs:

    6

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Output Characteristics:

    3-STATE

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    TSSOP

  • Package Equivalence Code:

    TSSOP28,.25

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE, THIN PROFILE, SHRINK PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Qualification Status:

    Not Qualified

  • Same Edge Skew-Max (tskwd):

    0.05 ns

  • Seated Height-Max:

    1.2 mm

  • Supply Voltage-Max (Vsup):

    3.465 V

  • Supply Voltage-Min (Vsup):

    3.135 V

  • Supply Voltage-Nom (Vsup):

    3.3 V

  • Surface Mount:

    YES

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Matte Tin (Sn) - annealed

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.65 mm

  • Terminal Position:

    DUAL

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    4.4 mm

9DB633AGILFT Frequently Asked Questions (FAQs)

  • Renesas provides a recommended PCB layout guide for the 9DB633AGILFT, which includes guidelines for thermal vias, copper pours, and component placement to ensure optimal thermal performance.
  • Renesas recommends a specific power sequencing procedure to ensure proper startup and operation of the device. This involves powering up the VCC and VDD pins in a specific order, followed by the AVDD and DVDD pins.
  • Renesas recommends using 0.1uF and 10uF decoupling capacitors for the VCC, VDD, AVDD, and DVDD pins, placed as close to the device as possible to minimize noise and ensure stable operation.
  • The 9DB633AGILFT has multiple low-power modes, including sleep and shutdown modes. To configure the device for low-power mode, use the Power Management Interface (PMI) to control the power modes and clock gating.
  • The 9DB633AGILFT has a maximum junction temperature of 150°C. To ensure reliable operation, it's essential to design a thermal management system that keeps the device within the recommended operating temperature range.

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9DB633AGILFT Overview

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