AD1846JP footprint, schematic symbol and 3D model by Analog Devices

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AD1846JP - Analog Devices PCB footprint - Plastic Leaded Chip Carrier - Plastic Leaded Chip Carrier - AD1846JP

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Part Number AD1846JP
Manufacturer Analog Devices
Pin Count 68
Part Category Integrated Circuit
Package Category Plastic Leaded Chip Carrier
Footprint Name Plastic Leaded Chip Carrier - AD1846JP
Released Date Feb 16, 2023
Last Modified Date Mar 7, 2023 4:10 PM UTC
Pinout / Pin List Click Here (Member Only)

AD1846JP Details

Manufacturer Part Number:
AD1846JP
Part Life Cycle Code:
Obsolete
Part Package Code:
LCC
Package Description:
PLASTIC, LCC-68
Pin Count:
68
HTS Code:
8542.39.00.60
Manufacturer:
Analog Devices Inc
YTEOL:
0
Consumer IC Type:
CONSUMER CIRCUIT
JESD-30 Code:
S-PQCC-J68
JESD-609 Code:
e0
Length:
24.18 mm
Number of Functions:
1
Number of Terminals:
68
Operating Temperature-Max:
70 °C
Package Body Material:
PLASTIC/EPOXY
Package Code:
QCCJ
Package Equivalence Code:
LDCC68,1.0SQ
Package Shape:
SQUARE
Package Style:
CHIP CARRIER
Qualification Status:
Not Qualified
Seated Height-Max:
4.45 mm
Supply Current-Max:
120 mA
Supply Voltage-Max (Vsup):
5.25 V
Supply Voltage-Min (Vsup):
4.75 V
Surface Mount:
YES
Technology:
HYBRID
Temperature Grade:
COMMERCIAL
Terminal Finish:
TIN LEAD
Terminal Form:
J BEND
Terminal Pitch:
1.27 mm
Terminal Position:
QUAD
Width:
24.18 mm

AD1846JP Frequently Asked Questions (FAQs)

The recommended power-up sequence is to apply VCC first, followed by VDD, and then the digital signals. This ensures that the analog and digital sections of the device are powered up correctly.
To optimize performance in a noisy environment, use proper PCB layout techniques, such as separating analog and digital grounds, using decoupling capacitors, and shielding the device from electromagnetic interference (EMI). Additionally, consider using a low-pass filter on the analog input signals to reduce noise.
The maximum clock frequency that can be used with the AD1846JP is 50 MHz. However, the actual clock frequency used may be limited by the specific application and the quality of the clock signal.
To configure the AD1846JP for master mode operation, set the M/S pin high and ensure that the BCLK pin is connected to a valid clock signal. Additionally, configure the device's control registers to enable master mode operation.
The latency of the AD1846JP's analog-to-digital conversion process is approximately 2.5 clock cycles. This means that there is a delay of 2.5 clock cycles between the time the analog input signal is sampled and the time the digital output data is available.

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AD1846JP Overview

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About Analog Devices

Analog Devices Inc. is a global leader in the design and manufacturing of analog, mixed-signal, and digital signal processing integrated circuits and software solutions for the industrial, automotive, healthcare, communications industries. Analog Devices serves a diverse range of markets including industrial, automotive, healthcare, energy, aerospace, defense, and consumer electronics industries. Analog Devices’ product portfolio includes a wide range of ICs, modules, and subsystems.

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