AD6679BBPZ-500 - Analog Devices

AD6679BBPZ-500 Frequently Asked Questions (FAQs)

• What is the recommended PCB layout for optimal performance of the AD6679BBPZ-500?
  A 4-layer PCB with a solid ground plane and a separate analog ground plane is recommended. Keep the analog and digital sections separate, and use a common mode filter to reduce noise.
• How do I optimize the clocking scheme for the AD6679BBPZ-500?
  Use a low-jitter clock source, and ensure the clock frequency is within the recommended range (10 MHz to 40 MHz). Use a clock buffer to reduce clock skew and ensure a clean clock signal.
• What is the recommended power-up sequence for the AD6679BBPZ-500?
  Power up the analog supply (AVDD) first, followed by the digital supply (DVDD), and finally the clock signal. Ensure a monotonic power-up sequence to prevent latch-up.
• How do I handle the output data format of the AD6679BBPZ-500?
  The AD6679BBPZ-500 outputs 14-bit data in a 2's complement format. Ensure your digital signal processing (DSP) or microcontroller (MCU) can handle this format, or use a format converter if necessary.
• What is the recommended calibration procedure for the AD6679BBPZ-500?
  Perform a full-scale calibration after power-up, and re-calibrate every 10 minutes or when the temperature changes by more than 10°C. Use the CAL pin to initiate calibration.