AD9628BCPZ-105 - Analog Devices

AD9628BCPZ-105 Frequently Asked Questions (FAQs)

• What is the recommended PCB layout for the AD9628BCPZ-105 to minimize noise and ensure optimal performance?
  A 4-layer PCB with a solid ground plane and a separate analog and digital power plane is recommended. Keep the analog and digital signals separate and avoid crossing them over each other. Use a common mode filter and a low-pass filter to reduce noise.
• How do I optimize the clock input to the AD9628BCPZ-105 for best performance?
  Use a low-jitter clock source (<100 ps) and ensure the clock signal is properly terminated. Use a clock signal with a frequency that is an integer multiple of the sampling frequency to minimize jitter. Also, ensure the clock signal is properly filtered to remove any high-frequency noise.
• What is the recommended power-up sequence for the AD9628BCPZ-105?
  Power up the analog supply (AVDD) first, followed by the digital supply (DVDD), and then the clock signal. This ensures that the analog circuitry is powered up before the digital circuitry, which helps to prevent any potential latch-up conditions.
• How do I handle the output data from the AD9628BCPZ-105, especially when it comes to data alignment and formatting?
  The AD9628BCPZ-105 outputs data in a 12-bit parallel format. Ensure that the receiving device is properly aligned to receive the data. Use a FIFO or a data buffer to handle the data and ensure that it is properly formatted for further processing.
• What are some common mistakes to avoid when designing with the AD9628BCPZ-105?
  Common mistakes to avoid include not following the recommended PCB layout, not using a common mode filter, not properly terminating the clock signal, and not following the recommended power-up sequence. Also, ensure that the analog and digital supplies are properly decoupled and filtered.