A 4-layer PCB with a solid ground plane and a separate power plane is recommended. Keep the PLL loop filter components close to the device and use a star-configuration for the power supply lines to minimize noise.
Use the ADIsimPLL tool to design and optimize the PLL loop filter. The tool provides a graphical interface to enter the device parameters and generates a recommended loop filter component values.
The maximum frequency deviation is ±50% of the reference frequency. However, the actual deviation achievable depends on the specific application and the PLL loop filter design.
Use a low-ESR capacitor (e.g., 100nF) close to the device's power pins and a larger capacitor (e.g., 10uF) farther away. Ensure the power supply lines are decoupled from the analog and digital grounds.
Use a 3-wire serial interface (SPI) to program the device. The recommended programming sequence is: reset, load the desired frequency, and then enable the PLL.
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ADF4368BCCZ Overview
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