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ADP1713AUJZ-3.3-R7 - Analog Devices

Description: ANALOG DEVICES - ADP1713AUJZ-3.3-R7 - LDO, FIXED, 3.3V, 0.3A, TSOT-5

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ADP1713AUJZ-3.3-R7 - Analog Devices PCB footprint - SOT23 (5-Pin) - SOT23 (5-Pin) - UJ-5 (TSOT)-ren1
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ADP1713AUJZ-3.3-R7 - Analog Devices  - 3D model - SOT23 (5-Pin) - UJ-5 (TSOT)-ren1
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ADP1713AUJZ-3.3-R7 Details

  • Manufacturer Part Number:

    ADP1713AUJZ-3.3-R7

  • Brand Name:

    Analog Devices Inc

  • Pbfree Code:

    No

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    TSOT

  • Package Description:

    LEAD FREE, MO-193AB, TSOT-5

  • Pin Count:

    5

  • Manufacturer Package Code:

    UJ-5

  • Country Of Origin:

    Malaysia

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Analog Devices Inc

  • YTEOL:

    10

  • Adjustability:

    FIXED

  • Dropout Voltage1-Max:

    0.27 V

  • Dropout Voltage1-Nom:

    0.17 V

  • Input Voltage Absolute-Max:

    6 V

  • Input Voltage-Max:

    5.5 V

  • Input Voltage-Min:

    2.5 V

  • JESD-30 Code:

    R-PDSO-G5

  • JESD-609 Code:

    e3

  • Length:

    2.9 mm

  • Line Regulation-Max:

    0.014%

  • Load Regulation-Max:

    0.0383%

  • Moisture Sensitivity Level:

    1

  • Number of Functions:

    1

  • Number of Outputs:

    1

  • Number of Terminals:

    5

  • Operating Temperature TJ-Max:

    125 °C

  • Operating Temperature TJ-Min:

    -40 °C

  • Output Current1-Max:

    0.3 A

  • Output Voltage1-Max:

    3.366 V

  • Output Voltage1-Min:

    3.234 V

  • Output Voltage1-Nom:

    3.3 V

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    VSSOP

  • Package Equivalence Code:

    TSOP5/6,.11,37

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH

  • Packing Method:

    TR

  • Peak Reflow Temperature (Cel):

    260

  • Qualification Status:

    Not Qualified

  • Regulator Type:

    FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR

  • Seated Height-Max:

    1 mm

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Terminal Finish:

    Matte Tin (Sn)

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.95 mm

  • Terminal Position:

    DUAL

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Voltage Tolerance-Max:

    2%

  • Width:

    1.6 mm

ADP1713AUJZ-3.3-R7 Frequently Asked Questions (FAQs)

  • A good PCB layout for the ADP1713 involves keeping the input and output capacitors close to the device, using a solid ground plane, and minimizing trace lengths and widths to reduce noise and EMI.
  • To ensure stability, it's essential to follow the recommended component values and PCB layout, and to add a compensation capacitor (Ccomp) between the COMP pin and GND. The value of Ccomp depends on the output capacitor value and the desired stability margin.
  • The ADP1713 can handle input voltages up to 15V, but it's recommended to operate within the specified input voltage range (5.5V to 14V) for optimal performance and reliability.
  • The ADP1713 is rated for operation up to 125°C, but its performance and reliability may degrade at high temperatures. It's essential to consider the thermal design and heat dissipation in the system to ensure reliable operation.
  • The output voltage ripple of the ADP1713 can be calculated using the formula: ΔVout = (Iout * ESL) / (Cout * fsw), where ESL is the equivalent series inductance of the output capacitor, Cout is the output capacitance, and fsw is the switching frequency.

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ADP1713AUJZ-3.3-R7 Overview

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About Analog Devices

Analog Devices Inc. is a global leader in the design and manufacturing of analog, mixed-signal, and digital signal processing integrated circuits and software solutions for the industrial, automotive, healthcare, communications industries. Analog Devices serves a diverse range of markets including industrial, automotive, healthcare, energy, aerospace, defense, and consumer electronics industries. Analog Devices’ product portfolio includes a wide range of ICs, modules, and subsystems.

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