ASMT-QWBF-NKL0E footprint, schematic symbol and 3D model by Avago Technologies

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ASMT-QWBF-NKL0E Details

The recommended power-up sequence is to apply VCC first, followed by VDD, and then the input clock signal.
Allow at least 10ms for the device to stabilize after power-up before using the output clocks.
The maximum input clock frequency is 350 MHz.
Yes, the device supports differential input clocks, such as LVPECL or LVDS.
The output clock frequencies are configured using the SEL0 and SEL1 pins, which select one of four possible output frequencies.

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