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AT25SF641-SUB-T - Adesto Technologies

Description: NOR Flash 64M 2.7V-3.6V SPI 104MHz IND TEMP

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AT25SF641-SUB-T - Adesto Technologies PCB footprint - Small Outline Packages - Small Outline Packages - SOP-8-
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AT25SF641-SUB-T - Adesto Technologies  - 3D model - Small Outline Packages - SOP-8-
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AT25SF641-SUB-T Details

  • Manufacturer Part Number:

    AT25SF641-SUB-T

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Transferred

  • Package Description:

    SOIC-8

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.32.00.51

  • Manufacturer:

    Adesto Technologies Corporation

  • Clock Frequency-Max (fCLK):

    104 MHz

  • JESD-30 Code:

    S-PDSO-G8

  • JESD-609 Code:

    e1

  • Length:

    5.28 mm

  • Memory Density:

    67108864 bit

  • Memory IC Type:

    FLASH

  • Memory Width:

    8

  • Number of Functions:

    1

  • Number of Terminals:

    8

  • Number of Words:

    8388608 words

  • Number of Words Code:

    8000000

  • Operating Mode:

    SYNCHRONOUS

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    8MX8

  • Output Characteristics:

    3-STATE

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    SOP

  • Package Equivalence Code:

    SOP8,.3

  • Package Shape:

    SQUARE

  • Package Style:

    SMALL OUTLINE

  • Parallel/Serial:

    SERIAL

  • Programming Voltage:

    2.7 V

  • Seated Height-Max:

    2.16 mm

  • Serial Bus Type:

    QSPI

  • Supply Voltage-Max (Vsup):

    1.95 V

  • Supply Voltage-Min (Vsup):

    1.65 V

  • Supply Voltage-Nom (Vsup):

    1.8 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    TIN SILVER COPPER

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    1.27 mm

  • Terminal Position:

    DUAL

  • Type:

    NOR TYPE

  • Width:

    5.28 mm

  • Write Protection:

    HARDWARE/SOFTWARE

AT25SF641-SUB-T Frequently Asked Questions (FAQs)

  • The recommended operating voltage range for the AT25SF641-SUB-T is 2.7V to 3.6V.
  • The HOLD pin should be pulled high during power-up and power-down sequences to prevent unwanted writes to the device.
  • The AT25SF641-SUB-T supports up to 100,000 erase cycles.
  • Wear leveling can be implemented by distributing write cycles across the entire memory space, using techniques such as dynamic wear leveling or static wear leveling.
  • The WP pin is used to prevent writes to the status register and the memory array. When WP is low, the device is in write-protect mode.

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