AT25SF641B-SHB-T footprint, schematic symbol and 3D model by Adesto Technologies

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AT25SF641B-SHB-T Details

The AT25SF641B-SHB-T supports up to 100,000 erase cycles.
The AT25SF641B-SHB-T uses a page write buffer to handle page write operations. The buffer is 128 bytes long, and the device can perform a page write operation in 1.5 ms (typical).
The WP# (Write Protect) pin is used to prevent accidental writes to the device. When the WP# pin is low, the entire memory array is protected from writes.
The AT25SF641B-SHB-T has a built-in power-on reset circuit that ensures the device is in a known state after power-up. The device also has a POR (Power-On Reset) timer that delays the device's readiness after power-up by 10 ms (typical).
The recommended operating voltage range for the AT25SF641B-SHB-T is 2.7V to 3.6V.

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