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AT45DB641E-SHN-T - Adesto Technologies

Description: ADESTO TECHNOLOGIES - AT45DB641E-SHN-T - FLASH MEMORY, 64MBIT, -40 TO 85DEG C

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AT45DB641E-SHN-T - Adesto Technologies PCB footprint - Small Outline Packages - Small Outline Packages - 8S2
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AT45DB641E-SHN-T Details

  • Manufacturer Part Number:

    AT45DB641E-SHN-T

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Transferred

  • Part Package Code:

    SOIC

  • Package Description:

    SOIC-8

  • Pin Count:

    8

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.32.00.51

  • Manufacturer:

    Adesto Technologies Corporation

  • Clock Frequency-Max (fCLK):

    85 MHz

  • JESD-30 Code:

    R-PDSO-G8

  • JESD-609 Code:

    e4

  • Length:

    5.29 mm

  • Memory Density:

    67108864 bit

  • Memory IC Type:

    FLASH

  • Memory Width:

    1

  • Moisture Sensitivity Level:

    1

  • Number of Functions:

    1

  • Number of Terminals:

    8

  • Number of Words:

    67108864 words

  • Number of Words Code:

    64000000

  • Operating Mode:

    SYNCHRONOUS

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    64MX1

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    SOP

  • Package Equivalence Code:

    SOP8,.3

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Parallel/Serial:

    SERIAL

  • Programming Voltage:

    1.8 V

  • Seated Height-Max:

    2.16 mm

  • Supply Voltage-Max (Vsup):

    3.6 V

  • Supply Voltage-Min (Vsup):

    1.7 V

  • Supply Voltage-Nom (Vsup):

    2.3 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    NICKEL PALLADIUM GOLD

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    1.27 mm

  • Terminal Position:

    DUAL

  • Width:

    5.24 mm

AT45DB641E-SHN-T Frequently Asked Questions (FAQs)

  • The recommended operating voltage range for the AT45DB641E-SHN-T is 2.7V to 3.6V.
  • The HOLD pin should be pulled high during power-up and power-down sequences to prevent unwanted writes to the device.
  • The WP (Write Protect) pin is used to prevent writes to the entire device or a specific sector. To use it, tie the WP pin to VCC to enable write protection or to GND to disable it.
  • To perform a sector erase, send the Sector Erase command (0x50) followed by the sector address. The device will then erase the specified sector.
  • The AT45DB641E-SHN-T supports up to 100,000 erase cycles per sector.

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