BD750L2FP3-CE2 footprint, schematic symbol and 3D model by ROHM Semiconductor

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Part Number BD750L2FP3-CE2
Manufacturer ROHM Semiconductor
Pin Count 4
Part Category Integrated Circuit
Package Category SOT223 (3-Pin)
Footprint Name SOT223 (3-Pin) - SOT223-4(F)_1
Released Date Jul 23, 2018
Last Modified Date Mar 7, 2023 4:10 PM UTC
Pinout / Pin List Click Here (Member Only)

BD750L2FP3-CE2 Details

Manufacturer Part Number:
BD750L2FP3-CE2
Rohs Code:
Yes
Part Life Cycle Code:
Active
ECCN Code:
EAR99
HTS Code:
8542.39.00.60
Factory Lead Time:
20 Weeks
Manufacturer:
ROHM Semiconductor
YTEOL:
6.2
Adjustability:
FIXED
Dropout Voltage1-Max:
0.7 V
Dropout Voltage1-Nom:
0.4 V
Input Voltage Absolute-Max:
50 V
Input Voltage-Max:
45 V
Input Voltage-Min:
5.8 V
JESD-30 Code:
R-PDSO-G4
JESD-609 Code:
e3
Length:
6.53 mm
Line Regulation-Max:
0.02%
Load Regulation-Max:
0.02%
Number of Functions:
1
Number of Outputs:
1
Number of Terminals:
4
Operating Temperature TJ-Max:
150 °C
Operating Temperature-Max:
125 °C
Operating Temperature-Min:
-40 °C
Output Current1-Max:
0.2 A
Output Voltage1-Max:
5.1 V
Output Voltage1-Min:
4.9 V
Output Voltage1-Nom:
5 V
Package Body Material:
PLASTIC/EPOXY
Package Code:
SOP
Package Equivalence Code:
SOT-223
Package Shape:
RECTANGULAR
Package Style:
SMALL OUTLINE
Packing Method:
TR
Qualification Status:
Not Qualified
Regulator Type:
FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
Screening Level:
AEC-Q100
Seated Height-Max:
1.8 mm
Surface Mount:
YES
Technology:
CMOS
Terminal Finish:
Tin (Sn)
Terminal Form:
GULL WING
Terminal Pitch:
2.3 mm
Terminal Position:
DUAL
Voltage Tolerance-Max:
2%
Width:
3.43 mm

BD750L2FP3-CE2 Frequently Asked Questions (FAQs)

A 2-layer or 4-layer PCB with a thermal relief pattern and a solid ground plane is recommended. The device should be placed near a thermal pad or a heat sink to ensure efficient heat dissipation.
To ensure stable operation with a high-ESR output capacitor, add a 1-10nF ceramic capacitor in parallel with the output capacitor to reduce the overall ESR. Additionally, ensure the output capacitor is placed close to the device and the PCB layout is optimized for low impedance.
A 10-22uF ceramic or electrolytic capacitor with a low ESR (< 1 ohm) is recommended for the input capacitor. The capacitor should be placed close to the device and the PCB layout should be optimized for low impedance.
Use a voltage supervisor or a reset IC to monitor the input voltage and reset the device if it falls outside the recommended operating range. Additionally, consider adding overvoltage protection (OVP) and undervoltage protection (UVP) circuits to prevent damage to the device.
Keep the power traces short and wide, and use a star topology to minimize impedance. Place the input capacitor, output capacitor, and inductor close to the device, and ensure the PCB layout is optimized for low impedance and minimal noise coupling.

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BD750L2FP3-CE2 Overview

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BD750L2FP3-CE2 - ROHM Semiconductor

BD750L2FP3-CE2 Details

BD750L2FP3-CE2 Frequently Asked Questions (FAQs)

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