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BD750L5FP-CE2 - ROHM Semiconductor

Description: Ultra Low Quiescent Current LDO Regulator: The BD7xxL5FP-C Series are low quiescent regulators featuring 50V absolute maximum voltage, and output voltage accuracy of ±2%, 500mA output current and 6µA (Typ.) current consumption. There regulators are therefore ideal for applications requiring a direct connection to the battery and a low current consumption. Ceramic capacitors can be used for compensation of the output capacitor phase.

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BD750L5FP-CE2 - ROHM Semiconductor PCB footprint - Other - Other - TO252-3 (Dry pack)
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BD750L5FP-CE2 - ROHM Semiconductor  - 3D model - Other - TO252-3 (Dry pack)
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BD750L5FP-CE2 Details

  • Manufacturer Part Number:

    BD750L5FP-CE2

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.60

  • Manufacturer:

    ROHM Semiconductor

  • YTEOL:

    6.7

  • Adjustability:

    FIXED

  • Dropout Voltage1-Max:

    0.5 V

  • Dropout Voltage1-Nom:

    0.25 V

  • Input Voltage Absolute-Max:

    50 V

  • Input Voltage-Max:

    45 V

  • Input Voltage-Min:

    8 V

  • JESD-30 Code:

    R-PSSO-G2

  • JESD-609 Code:

    e3

  • Length:

    6.5 mm

  • Line Regulation-Max:

    0.02%

  • Load Regulation-Max:

    0.02%

  • Number of Functions:

    1

  • Number of Outputs:

    1

  • Number of Terminals:

    2

  • Operating Temperature TJ-Max:

    150 °C

  • Operating Temperature-Max:

    125 °C

  • Operating Temperature-Min:

    -40 °C

  • Output Current1-Max:

    0.5 A

  • Output Voltage1-Max:

    5.1 V

  • Output Voltage1-Min:

    4.9 V

  • Output Voltage1-Nom:

    5 V

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    TO-252

  • Package Equivalence Code:

    SMSIP3H,.38,90TB

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Packing Method:

    TR, EMBOSSED

  • Peak Reflow Temperature (Cel):

    260

  • Qualification Status:

    Not Qualified

  • Regulator Type:

    FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR

  • Screening Level:

    AEC-Q100

  • Seated Height-Max:

    2.5 mm

  • Surface Mount:

    YES

  • Terminal Finish:

    Tin (Sn)

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    2.3 mm

  • Terminal Position:

    SINGLE

  • Time@Peak Reflow Temperature-Max (s):

    10

  • Voltage Tolerance-Max:

    2%

  • Width:

    5.5 mm

BD750L5FP-CE2 Frequently Asked Questions (FAQs)

  • A recommended PCB layout for optimal thermal performance would be to have a large copper area on the bottom layer connected to the thermal pad of the IC, and to use thermal vias to dissipate heat to the top layer. Additionally, it's recommended to have a solid ground plane on the top layer to reduce thermal resistance.
  • To ensure stable operation with a high-ESR output capacitor, it's recommended to add a small ceramic capacitor (e.g. 10nF) in parallel with the output capacitor to reduce the overall ESR. Additionally, the output capacitor should be placed close to the IC to minimize parasitic inductance.
  • The maximum allowed voltage on the EN pin is 6V. Exceeding this voltage may damage the IC. It's recommended to use a voltage divider or a level shifter if the enable signal is coming from a higher voltage domain.
  • The output voltage ripple can be calculated using the following formula: ΔVout = (Iout * ESR) / (f * C), where Iout is the output current, ESR is the equivalent series resistance of the output capacitor, f is the switching frequency, and C is the output capacitance.
  • The recommended input capacitor type is a ceramic capacitor with a value of 10uF to 22uF, depending on the input voltage and current requirements. A low-ESR capacitor is recommended to minimize voltage ripple and ensure stable operation.

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