The recommended soldering temperature profile for the CL31F104ZACNBNC is a peak temperature of 260°C for 10-30 seconds, with a ramp-up rate of 3°C/s and a ramp-down rate of 6°C/s.
The ESR of the CL31F104ZACNBNC is typically around 50 mΩ, which is relatively low. This means that the capacitor has a low impedance and can handle high-frequency signals with minimal energy loss.
The maximum operating voltage derating for the CL31F104ZACNBNC is 80% of the rated voltage, which is 16V for this specific part. This means that the capacitor should not be operated above 12.8V to ensure reliable performance and longevity.
The capacitance of the CL31F104ZACNBNC decreases with increasing temperature, with a temperature coefficient of -55 ppm/°C. This means that the capacitance will decrease by approximately 0.055% for every 1°C increase in temperature.
The recommended land pattern and pad layout for the CL31F104ZACNBNC can be found in the Samsung Electro-Mechanics application note or in the IPC-7351 standard. A general guideline is to use a land pattern with a diameter of 1.5-2.5 mm and a pad spacing of 0.5-1.5 mm.
Trust Checks
No trust score is available for this model.
Trust Score Unavailable
Sponsored
CL31F104ZACNBNC Overview
Use the download button to access the CL31F104ZACNBNC 3D model. You can still request or build the schematic symbol and PCB footprint by using the respective build or request forms on this page.
To find more CAD model downloads similar to this part, try a partial part number search, like CL31F,
or try a keyword search, such as Array/Network Capacitors
